Diandian Zhang

Diandian Zhang, Han Zhang, Jerónimo Castrillón, Torsten Kempf, Bart Vanthournout, Gerd Ascheid, Rainer Leupers: Optimized Communication Architecture of MPSoCs with a Hardware Scheduler: A System-Level Analysis. IJERTCS 2(3): 1-20 (2011)

Anupam Chattopadhyay, Arnab Sinha, Diandian Zhang, Rainer Leupers, Gerd Ascheid, Heinrich Meyr: Integrated verification approach during ADL-driven processor design. Microelectronics Journal 40(7): 1111-1123 (2009)

David Kammler, Diandian Zhang, Peter Schwabe, Hanno Scharwächter, Markus Langenberg, Dominik Auras, Gerd Ascheid, Rudolf Mathar: Designing an ASIP for Cryptographic Pairings over Barreto-Naehrig Curves. CHES 2009: 254-271

Jerónimo Castrillón, Diandian Zhang, Torsten Kempf, Bart Vanthournout, Rainer Leupers, Gerd Ascheid: Task management in MPSoCs: An ASIP approach. ICCAD 2009: 587-594

David Kammler, Diandian Zhang, Peter Schwabe, Hanno Scharwächter, Markus Langenberg, Dominik Auras, Gerd Ascheid, Rainer Leupers, Rudolf Mathar, Heinrich Meyr: Designing an ASIP for Cryptographic Pairings over Barreto-Naehrig Curves. IACR Cryptology ePrint Archive 2009: 56 (2009)

Diandian Zhang, Anupam Chattopadhyay, David Kammler, Ernst Martin Witte, Gerd Ascheid, Rainer Leupers, Heinrich Meyr: Power-efficient Instruction Encoding Optimization for Various Architecture Classes. JCP 3(3): 25-38 (2008)

Anupam Chattopadhyay, Diandian Zhang, David Kammler, Ernst Martin Witte: Power-efficient Instruction Encoding Optimization for Embedded Processors. VLSI Design 2007: 595-600

Anupam Chattopadhyay, Arnab Sinha, Diandian Zhang, Rainer Leupers, Gerd Ascheid, Heinrich Meyr: Integrated Verification Approach during ADL-Driven Processor Design. IEEE International Workshop on Rapid System Prototyping 2006: 110-118