Wei Zhang

Virginia Commonwealth University / Southern Illinois University, Ph.D: Pennsylvania State University

other persons with the same name:

• Wei Zhang
• Wei Zhang 0001 - University of New South Wales / Hong Kong University of Science & Technology
• Wei Zhang 0003 - QualComm / Georgia Insitute of Technology
• Wei Zhang 0004 - Institute of Software, Peking University
• Wei Zhang 0005 - Guandong University of Technology
• Wei Zhang 0006 - Department of Industrial Engineering, Tsinghua University
• Wei Zhang 0007 - University of Alberta
• Wei Zhang 0008 - Microsoft Live Search, PhD: University of Illinois at Chicago
• Wei Zhang 0009 - Xidian University / Key Laboratory of Intelligent Perception and Image Understanding of Ministry of Education of China
• Wei Zhang 0010 - Department of Information Engineering, The Chinese University of Hong Kong
• Wei Zhang 0011 - The University of Texas M. D. Anderson Cancer Center
• Wei Zhang 0012 - Nanyang Technological University / Princeton University
• Wei Zhang 0013 - Ohio State University / Purdue
• Wei Zhang 0014 - Google / Oregon State University
• Wei Zhang 0015 - Boeing Research / Oregon State University
• Wei Zhang 0016 - Fudan University
• Wei Zhang 0017 - Harbin Institute of Technology
• Wei Zhang 0018 - SAIC / George Mason University
• Wei Zhang 0019 - College of Chemistry and Molecular Engineering, Peking University
• Wei Zhang 0020 - Florida State University
• Wei Zhang 0021 - Image and Video Processing Laboratory, Department of Electronic Engineering, The Chinese University of Hong Kong
• Wei Zhang 0022 - University of Wisconsin-Madison
• Wei Zhang 0023 - Quantlab Financial / Robotics Insitute, Carnegie Mellon University
• Wei Zhang 0024 - Worcester Polytechnic Institute
• Wei Zhang 0025 - University of Windsor, Canada / Shanghai Jiao Tong University
• Wei Zhang 0026 - College of Management and Economics, Tianjin University
• Wei Zhang 0027 - National University of Defence Technology, ChangSha
• Wei Zhang 0028 - School of Electrical Engineering and Automation, Henan Polytechni University
• Wei Zhang 0029 - Department of Automation, Shanghai Jiao Tong University
• Wei Zhang 0030 - University of Sussex
• Wei Zhang 0031 - School of Computer Science & Technology, Tianjin University
• Wei Zhang 0032 - University of Minnesota, Minneapolis, MN, USA
• Wei Zhang 0033 - University of Science and Technology of China, Hefei
• Wei Zhang 0034 - McGill University
• Wei Zhang 0035 - School of Management, University of Massachussetts, Boston
• Wei Zhang 0036 - FernUniversität Hagen
• Wei Zhang 0037 - Rockwell Collions Government Systems / University of Ottawa
• Wei Zhang 0038 - National University of Singapore
• Wei Zhang 0039 - Illinois Institute of Technology
• Wei Zhang 0040 - Network Architecture Lab, Tsinghua University
• Wei Zhang 0041 - Department of Computer Science and Engineering, Texas A&M University, TX, USA
• Wei Zhang 0042 - China University of Mining and Technology, Xuzhou, China
• Wei Zhang 0043 - Institute of Computing Technology, Chinese Academy of Sciences, Beijing, China
• Wei Zhang 0044 - University of Virginia, Charlottesville, Virginia, USA
• Wei Zhang 0045 - Institute of Electronic Engineering, China Academy of Engineering Physics (CAEP), Mianyang, China
• Wei Zhang 0046 - School of Psychology, South China Normal University, Guangzhou, Guangdong, China
• Wei Zhang 0047 - Digital Resources and Services Department, National Library of China, Beijing, China
• Wei Zhang 0048 - Department of Geography and Resource Management, The Chinese University of Hong Kong, Shatin, Hong Kong
• Wei Zhang 0049 - Shandong Provincial Key Laboratory of Computer Networks, Shandong Computer Science Center, Jinan, China
• Wei Zhang 0050 - College of Science, Xi'an Jiaotong University, Xi'an, Shanxi, China
• Wei Zhang 0051 - Oracle Corporation, Redwood City, USA

	2013
j37		Yiqiang Ding, Lan Wu, Wei Zhang: Bounding Worst-Case DRAM Performance on Multicore Processors. JCSE 7(1): 53-66 (2013)
j36		Yiqiang Ding, Wei Zhang: Multicore Real-Time Scheduling to Reduce Inter-Thread Cache Interferences. JCSE 7(1): 67-80 (2013)
	2012
j35		Yiqiang Ding, Wei Zhang: Multicore-Aware Code Co-Positioning to Reduce WCET on Dual-Core Processors with Shared Instruction Caches. JCSE 6(1): 12-25 (2012)
j34		Yu Sun, Wei Zhang: Time-Predictable Java Dynamic Compilation on Multicore Processors. JCSE 6(1): 26-38 (2012)
j33		Yu Sun, Wei Zhang: On-line Trace Based Automatic Parallelization of Java Programs on Multicore Platforms. JCSE 6(2): 105-118 (2012)
j32		Wei Zhang, Jun Yan: Static Timing Analysis of Shared Caches for Multicore Processors. JCSE 6(4): 267-278 (2012)
j31		Yiqiang Ding, Wei Zhang: Architectural time-predictability factor (ATF): a metric to evaluate time predictability of processors. SIGBED Review 9(4): 6-15 (2012)
j30		Lan Wu, Wei Zhang: A Model Checking Based Approach to Bounding Worst-Case Execution Time for Multicore Processors. ACM Trans. Embedded Comput. Syst. 11(S2): 56 (2012)
c49		Yu Liu, Wei Zhang: Exploiting SPM-aware Scheduling on EPIC architectures for high-performance real-time systems. HPEC 2012: 1-2
c48		Yu Liu, Wei Zhang: Exploiting multi-level scratchpad memories for time-predictable multicore computing. ICCD 2012: 61-66
	2011
j29		Abhishek Pillai, Wei Zhang: Exploiting Instruction Reuse to Improve the Performance of Dual Instruction Execution. Journal of Circuits, Systems, and Computers 20(5): 899-913 (2011)
j28		Jun Yan, Wei Zhang: Bounding Worst-Case Performance for Multi-Core Processors with Shared L2 Instruction Caches. JCSE 5(1): 1-18 (2011)
j27		Jun Yan, Wei Zhang: Computing and Reducing Transient Error Propagation in Registers. JCSE 5(2): 121-130 (2011)
j26		Jun Yan, Wei Zhang: An Interference Matrix Based Approach to Bounding Worst-Case Inter-Thread Cache Interferences and WCET for Multi-Core Processors. JCSE 5(2): 131-140 (2011)
c47		Yu Sun, Wei Zhang: On-Line Trace Based Automatic Parallelization of Java Programs on Multicore Platforms. Interaction between Compilers and Computer Architectures 2011: 35-43
c46		Yu Liu, Wei Zhang: Static Worst-Case Lifetime Estimation of Vigil Net. GreenCom 2011: 1-8
c45		Yiqiang Ding, Wei Zhang: Multicore-Aware Code Positioning to Improve Worst-Case Performance. ISORC 2011: 225-232
c44		Yu Liu, Wei Zhang: Exploiting time predictable two-level scratchpad memory for real-time systems. SAC 2011: 395-396
c43		Yu Liu, Wei Zhang: Stack distance based worst-case instruction cache performance analysis. SAC 2011: 723-728
	2010
j25		Jun Yan, Wei Zhang: Design and implementation of hybrid multicore simulators. IJES 4(3/4): 270-275 (2010)
j24		Wei Zhang: Replica victim caching to improve cache reliability against transient errors. IJHPSA 2(3/4): 229-239 (2010)
j23		Shu-Hui Yin, Yufang Liu, Wei Zhang, Ming-Xing Guo, Peng Song: Time-dependent density functional theory study on the hydrogen bonding-induced twisted intramolecular charge-transfer excited states of 2-(4'-N, N-dimethylaminophenyl)imidazo[4, 5-b]pyridine. Journal of Computational Chemistry 31(10): 2056-2062 (2010)
j22		Yu Liu, Wei Zhang, Kemal Akkaya: Static Worst-Case Energy and Lifetime Estimation of Wireless Sensor Networks. JCSE 4(2): 128-152 (2010)
j21		Yiqiang Ding, Wei Zhang: Loop-Based Instruction Prefetching to Reduce the Worst-Case Execution Time. IEEE Trans. Computers 59(6): 855-864 (2010)
c42		Satya Mohan Raju Gudidevuni, Wei Zhang: A time-predictable dual-core prototype on FPGA. ACM Southeast Regional Conference 2010: 7
c41		Yiqiang Ding, Wei Zhang: Improving the static real-time scheduling on multicore processors by reducing worst-case inter-thread cache interferences. ACM Southeast Regional Conference 2010: 108
c40		Jun Yan, Wei Zhang: Time-Predictable L2 Cache Design for High-Performance Real-Time Systems. RTCSA 2010: 357-366
	2009
j20		Yu Sun, Wei Zhang: Improving Java performance and energy dissipation through efficient code caching. Design Autom. for Emb. Sys. 13(3): 179-192 (2009)
j19		Wei Zhang: Computing and Minimizing Cache Vulnerability to Transient Errors. IEEE Design & Test of Computers 26(2): 44-51 (2009)
j18		Yu Sun, Wei Zhang: Studying Energy-Oriented Dynamic Optimizations in Java Virtual Machines. Journal of Circuits, Systems, and Computers 18(1): 103-120 (2009)
j17		Yiqiang Ding, Jun Yan, Wei Zhang: Optimizing Instruction Prefetching to Improve Worst-Case Performance for Real-Time Applications. JCSE 3(1): 59-71 (2009)
j16		Yu Liu, Wei Zhang: Bounding Worst-Case Data Cache Performance by Using Stack Distance. JCSE 3(4): 195-215 (2009)
c39		Yu Liu, Wei Zhang, Kemal Akkaya: Static worst-case energy and lifetime estimation of wireless sensor networks. IPCCC 2009: 17-24
c38		Yu Sun, Wei Zhang: Exploiting Multi-core Processors to Improve Time Predictability for Real-Time Java Computing. RTCSA 2009: 447-454
c37		Wei Zhang, Jun Yan: Accurately Estimating Worst-Case Execution Time for Multi-core Processors with Shared Direct-Mapped Instruction Caches. RTCSA 2009: 455-463
c36		Yu Liu, Wei Zhang: Exploiting stack distance to estimate worst-case data cache performance. SAC 2009: 1979-1983
	2008
j15		Jun Yan, Wei Zhang: A time-predictable VLIW processor and its compiler support. Real-Time Systems 38(1): 67-84 (2008)
j14		Jun Yan, Wei Zhang: Exploiting virtual registers to reduce pressure on real registers. TACO 4(4) (2008)
j13		Jun Yan, Wei Zhang: Analyzing the worst-case execution time for instruction caches with prefetching. ACM Trans. Embedded Comput. Syst. 8(1) (2008)
c35		Yu Sun, Wei Zhang: Efficient code caching to improve performance and energy consumption for java applications. CASES 2008: 119-126
c34		Yu Sun, Wei Zhang: On the Energy Efficiency of Java Virtual Machine. ESA 2008: 29-33
c33		Yu Sun, Wei Zhang: Adaptive Drowsy Cache Control for Java Applications. EUC (1) 2008: 185-191
c32		Yu Sun, Wei Zhang: Improving code caching performance for Java applications. IPDPS 2008: 1-5
c31		Jun Yan, Wei Zhang: WCET Analysis for Multi-Core Processors with Shared L2 Instruction Caches. IEEE Real-Time and Embedded Technology and Applications Symposium 2008: 80-89
	2007
j12		Wei Zhang: Compiler-Assisted Leakage Energy Reduction for Cache Memories. Advances in Computers 69: 155-189 (2007)
j11		Jun Yan, Wei Zhang: Hybrid multi-core architecture for boosting single-threaded performance. SIGARCH Computer Architecture News 35(1): 141-148 (2007)
j10		Jun Yan, Wei Zhang: Evaluating instruction cache vulnerability to transient errors. SIGARCH Computer Architecture News 35(4): 21-28 (2007)
j9		Wei Zhang, Bramha Allu: Reducing branch predictor leakage energy by exploiting loops. ACM Trans. Embedded Comput. Syst. 6(2) (2007)
c30		Abhishek Pillai, Wei Zhang, Laurence Tianruo Yang: Exploring Functional Unit Design Space of VLIW Processors for Optimizing Both Performance and Energy Consumption. AINA Workshops (1) 2007: 792-797
c29		Mallik Kandala, Wei Zhang, Laurence Tianruo Yang: An Area-Efficient Approach to Improving Register File Reliability against Transient Errors. AINA Workshops (1) 2007: 798-803
c28		Abhishek Pillai, Wei Zhang, Dimitrios Kagaris: Detecting VLIW Hard Errors Cost-Effectively through a Software-Based Approach. AINA Workshops (1) 2007: 811-815
c27		Jun Yan, Wei Zhang: Virtual Registers: Reducing Register Pressure Without Enlarging the Register File. HiPEAC 2007: 57-70
c26		Wei Zhang, Gregory J. Zelinsky, Dimitris Samaras: Real-time Accurate Object Detection using Multiple Resolutions. ICCV 2007: 1-8
c25		Jun Yan, Wei Zhang: WCET analysis of instruction caches with prefetching. LCTES 2007: 175-184
	2006
j8		Wei Zhang: Compiler-guided next sub-bank prediction for reducing instruction cache leakage energy. J. Embedded Computing 2(1): 35-48 (2006)
j7		Bramha Allu, Wei Zhang: Reducing Instruction Translation Look-Aside Buffer Energy Through Compiler-Directed Resizing. J. Low Power Electronics 2(2): 140-147 (2006)
j6		Wei Zhang, Yuh-Fang Tsai, David Duarte, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin: Reducing dynamic and leakage energy in VLIW architectures. ACM Trans. Embedded Comput. Syst. 5(1): 1-28 (2006)
c24		Nagm Mohamed, Nazeih Botros, Wei Zhang: The Impact of Cache Organization in Optimizing Microprocessor Power Consumption. CDES 2006: 84-90
	2005
j5		Wei Zhang: Exploiting loop behavior for data cache leakage reduction. J. Embedded Computing 1(4): 501-508 (2005)
j4		Bramha Allu, Wei Zhang: Exploiting the replication cache to improve performance for multiple-issue microprocessors. SIGARCH Computer Architecture News 33(3): 63-71 (2005)
j3		Wei Zhang: Replication Cache: A Small Fully Associative Cache to Improve Data Cache Reliability. IEEE Trans. Computers 54(12): 1547-1555 (2005)
j2		Wei Zhang, Mahmut T. Kandemir, Mustafa Karaköy, Guangyu Chen: Reducing data cache leakage energy using a compiler-based approach. ACM Trans. Embedded Comput. Syst. 4(3): 652-678 (2005)
c23		Wei Zhang, Bing Yu, Gregory J. Zelinsky, Dimitris Samaras: Object Class Recognition Using Multiple Layer Boosting with Heterogeneous Features. CVPR (2) 2005: 323-330
c22		Wei Zhang: Computing Cache Vulnerability to Transient Errors and Its Implication. DFT 2005: 427-435
c21		Jun Yan, Wei Zhang: Compiler-guided register reliability improvement against soft errors. EMSOFT 2005: 203-209
c20		Gregory J. Zelinsky, Wei Zhang, Bing Yu, Xin Chen, Dimitris Samaras: The Role of Top-down and Bottom-up Processes in Guiding Eye Movements during Visual Search. NIPS 2005
c19		Wei Zhang, Hyejin Yang, Dimitris Samaras, Gregory J. Zelinsky: A Computational Model of Eye Movements during Object Class Detection. NIPS 2005
	2004
j1		Wei Zhang, Jie S. Hu, Vijay Degalahal, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin: Reducing instruction cache energy consumption using a compiler-based strategy. TACO 1(1): 3-33 (2004)
c18		Wei Zhang: Replica Victim Caching to Improve Reliability of In-Cache Replication. Asia-Pacific Computer Systems Architecture Conference 2004: 2-15
c17		Bramha Allu, Wei Zhang: Static next sub-bank prediction for drowsy instruction cache. CASES 2004: 124-131
c16		Wei Zhang, Bramha Allu: Loop-based leakage control for branch predictors. CASES 2004: 149-155
c15		Wei Zhang: Enhancing data cache reliability by the addition of a small fully-associative replication cache. ICS 2004: 12-19
c14		Wei Zhang: Compiler-Directed Data Cache Leakage Reduction. ISVLSI 2004: 305-306
	2003
c13		Wei Zhang, Mahmut T. Kandemir, Anand Sivasubramaniam, Mary Jane Irwin: Performance, energy, and reliability tradeoffs in replicating hot cache lines. CASES 2003: 309-317
c12		Wei Zhang, Guangyu Chen, Mahmut T. Kandemir, Mustafa Karaköy: Interprocedural optimizations for improving data cache performance of array-intensive embedded applications. DAC 2003: 887-892
c11		Hendra Saputra, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin, Richard R. Brooks, Soontae Kim, Wei Zhang: Masking the Energy Behavior of DES Encryption. DATE 2003: 10084-10089
c10		Mahmut T. Kandemir, Guangyu Chen, Wei Zhang, Ibrahim Kolcu: Data Space Oriented Scheduling in Embedded Systems. DATE 2003: 10416-10421
c9		Mahmut T. Kandemir, Wei Zhang, Mustafa Karaköy: Runtime Code Parallelization for On-Chip Multiprocessors. DATE 2003: 10510-10515
c8		Mahmut T. Kandemir, Ibrahim Kolcu, Wei Zhang: Implementation and Evaluation of an On-Demand Parameter-Passing Strategy for Reducing Energy. DATE 2003: 11058-11063
c7		Wei Zhang, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, Vivek De: Compiler Support for Reducing Leakage Energy Consumption. DATE 2003: 11146-11147
c6		Guilin Chen, Guangyu Chen, Ismail Kadayif, Wei Zhang, Mahmut T. Kandemir, Ibrahim Kolcu, Ugur Sezer: Compiler-Directed Management of Instruction Accesses. DSD 2003: 459-462
c5		Wei Zhang, Sudhanva Gurumurthi, Mahmut T. Kandemir, Anand Sivasubramaniam: ICR: In-Cache Replication for Enhancing Data Cache Reliability. DSN 2003: 291-300
c4		Wei Zhang, Mustafa Karaköy, Mahmut T. Kandemir, Guangyu Chen: A compiler approach for reducing data cache energy. ICS 2003: 76-85
	2002
c3		Jie S. Hu, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, Hendra Saputra, Wei Zhang: Compiler-directed cache polymorphism. LCTES-SCOPES 2002: 165-174
c2		Wei Zhang, Jie S. Hu, Vijay Degalahal, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin: Compiler-directed instruction cache leakage optimization. MICRO 2002: 208-218
	2001
c1		Wei Zhang, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin, David Duarte, Yuh-Fang Tsai: Exploiting VLIW schedule slacks for dynamic and leakage energy reduction. MICRO 2001: 102-113

Coauthor Index

Colors in the list of coauthors

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