Dajiang Zhou

Dajiang Zhou, Gang He, Wei Fei, Zhixiang Chen, Jinjia Zhou, Satoshi Goto: A 24.5-53.6pJ/pixel 4320p 60fps H.264/AVC intra-frame video encoder chip in 65nm CMOS. ASP-DAC 2013: 73-74

Zhixiang Chen, Xiao Peng, Xiongxin Zhao, Leona Okamura, Dajiang Zhou, Satoshi Goto: A 6.72-Gb/s, 8pJ/bit/iteration WPAN LDPC decoder in 65nm CMOS. ASP-DAC 2013: 87-88

Xiongxin Zhao, Xiao Peng, Zhixiang Chen, Dajiang Zhou, Satoshi Goto: A 115 mW 1 Gbps Bit-Serial Layered LDPC Decoder for WiMAX. IEICE Transactions 95-A(12): 2384-2391 (2012)

Xuena Bao, Dajiang Zhou, Peilin Liu, Satoshi Goto: An Advanced Hierarchical Motion Estimation Scheme With Lossless Frame Recompression and Early-Level Termination for Beyond High-Definition Video Coding. IEEE Transactions on Multimedia 14(2): 237-249 (2012)

Zhengyan Guo, Dajiang Zhou, Satoshi Goto: An optimized MC interpolation architecture for HEVC. ICASSP 2012: 1117-1120

Jinjia Zhou, Dajiang Zhou, Satoshi Goto: Interlaced asymmetric search range assignment for bidirectional motion estimation. ICIP 2012: 1557-1560

Heming Sun, Dajiang Zhou, Satoshi Goto: A Low-Complexity HEVC Intra Prediction Algorithm Based on Level and Mode Filtering. ICME 2012: 1085-1090

Dajiang Zhou, Jinjia Zhou, Jiayi Zhu, Peilin Liu, Satoshi Goto: A 2Gpixel/s H.264/AVC HP/MVC video decoder chip for Super Hi-Vision and 3DTV/FTV applications. ISSCC 2012: 224-226

Muchen Li, Jinjia Zhou, Dajiang Zhou, Xiao Peng, Satoshi Goto: De-blocking Filter Design for HEVC and H.264/AVC. PCM 2012: 273-284

Gang He, Dajiang Zhou, Jinjia Zhou, Tianruo Zhang, Satoshi Goto: A 530 Mpixels/s Intra Prediction Architecture for Ultra High Definition H.264/AVC Encoder. IEICE Transactions 94-C(4): 419-427 (2011)

Jinjia Zhou, Dajiang Zhou, Gang He, Satoshi Goto: Cache Based Motion Compensation Architecture for Quad-HD H.264/AVC Video Decoder. IEICE Transactions 94-C(4): 439-447 (2011)

Zhixiang Chen, Xiao Peng, Xiongxin Zhao, Leona Okamura, Dajiang Zhou, Satoshi Goto: A 6.72-Gb/s 8 pJ/bit/iteration IEEE 802.15.3c LDPC Decoder Chip. IEICE Transactions 94-A(12): 2587-2596 (2011)

Xun He, Xin Jin, Minghui Wang, Dajiang Zhou, Satoshi Goto: A 98 GMACs/W 32-Core Vector Processor in 65 nm CMOS. IEICE Transactions 94-A(12): 2609-2618 (2011)

Dajiang Zhou, Jinjia Zhou, Xun He, Jiayi Zhu, Ji Kong, Peilin Liu, Satoshi Goto: A 530 Mpixels/s 4096x2160@60fps H.264/AVC High Profile Video Decoder Chip. J. Solid-State Circuits 46(4): 777-788 (2011)

Xun He, Dajiang Zhou, Xin Jin, Satoshi Goto: A 98 GMACs/W 32-core vector processor in 65nm CMOS. ISLPED 2011: 373-378

Qian Xie, Qian He, Xiao Peng, Ying Cui, Zhixiang Chen, Dajiang Zhou, Satoshi Goto: A high parallel macro block level layered LDPC decoding architecture based on dedicated matrix reordering. SiPS 2011: 122-127

Ying Cui, Xiao Peng, Zhixiang Chen, Xiongxin Zhao, Yichao Lu, Dajiang Zhou, Satoshi Goto: Ultra low power QC-LDPC decoder with high parallelism. SoCC 2011: 142-145

Xianmin Chen, Peilin Liu, Dajiang Zhou, Jiayi Zhu, Xingguang Pan, Satoshi Goto: A High Performance and Low Bandwidth Multi-Standard Motion Compensation Design for HD Video Decoder. IEICE Transactions 93-C(3): 253-260 (2010)

Jinjia Zhou, Dajiang Zhou, Xun He, Satoshi Goto: A Bandwidth Optimized, 64 Cycles/MB Joint Parameter Decoder Architecture for Ultra High Definition H.264/AVC Applications. IEICE Transactions 93-A(8): 1425-1433 (2010)

Xuena Bao, Dajiang Zhou, Peilin Liu, Satoshi Goto: An advanced hierarchical motion estimation scheme with lossless frame recompression for ultra high definition video coding. ICME 2010: 820-825

Liu Song, Dajiang Zhou, Xin Jin, Satoshi Goto, Peilin Liu: An adaptive bandwidth reduction scheme for video coding. ISCAS 2010: 401-404

Zhixiang Chen, Xiongxin Zhao, Xiao Peng, Dajiang Zhou, Satoshi Goto: An early stopping criterion for decoding LDPC codes in WiMAX and WiFi standards. ISCAS 2010: 473-476

Xuena Bao, Dajiang Zhou, Satoshi Goto: A lossless frame recompression scheme for reducing DRAM power in video encoding. ISCAS 2010: 677-680

Jinjia Zhou, Dajiang Zhou, Gang He, Satoshi Goto: A Bandwidth Reduction Scheme and Its VLSI Implementation for H.264/AVC Motion Vector Decoding. PCM (2) 2010: 52-61

Gang He, Dajiang Zhou, Jinjia Zhou, Satoshi Goto: Intra prediction architecture for H.264/AVC QFHD encoder. PCS 2010: 450-453

Dajiang Zhou, Jinjia Zhou, Satoshi Goto: An Efficient Motion Vector Coding Scheme Based on Prioritized Reference Decision. IEICE Transactions 92-A(8): 1978-1985 (2009)

Dajiang Zhou, Jinjia Zhou, Jiayi Zhu, Satoshi Goto: A 48 Cycles/MB H.264/AVC Deblocking Filter Architecture for Ultra High Definition Applications. IEICE Transactions 92-A(12): 3203-3210 (2009)

Jinjia Zhou, Dajiang Zhou, Hang Zhang, Yu Hong, Peilin Liu, Satoshi Goto: A 136 cycles/MB, luma-chroma parallelized H.264/AVC deblocking filter for QFHD applications. ICME 2009: 1134-1137

Xianmin Chen, Peilin Liu, Jiayi Zhu, Dajiang Zhou, Satoshi Goto: Block-pipelining Cache for Motion Compensation in High Definition H.264/AVC Video Decoder. ISCAS 2009: 1069-1072

Dajiang Zhou, Jinjia Zhou, Satoshi Goto: Prioritized Reference Decision for Efficient Motion Vector Coding. ISCAS 2009: 1649-1652

Jiayi Zhu, Peilin Liu, Dajiang Zhou: An SDRAM controller optimized for high definition video coding application. ISCAS 2008: 3518-3521

Dajiang Zhou, Peilin Liu: A Hardware-Efficient Dual-Standard VLSI Architecture for MC Interpolation in AVS and H.264. ISCAS 2007: 2910-2913