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Hai Zhou
2010 – today
- 2013
[j43]Jian Sun, Yinghai Lu, Hai Zhou, Changhao Yan, Xuan Zeng: Post-routing layer assignment for double patterning with timing critical paths consideration. Integration 46(2): 153-164 (2013)- [j42]Peng Wu, Hai Zhou, Changhao Yan, Jun Tao, Xuan Zeng: An efficient method for gradient-aware dummy fill synthesis. Integration 46(3): 301-309 (2013)
- [j41]
- [c94]Yuankai Chen, Hai Zhou: Resource-constrained high-level datapath optimization in ASIP design. DATE 2013: 198-201
- [c93]Yinghai Lu, Hai Zhou: Retiming for Soft Error Minimization Under Error-Latching Window Constraints. DATE 2013: 1008-1013
- 2012
- [c92]Yuankai Chen, Hai Zhou: Buffer minimization in pipelined SDF scheduling on multi-core platforms. ASP-DAC 2012: 127-132
- [c91]
- [c90]
- [c89]Li Li, Peng Kang, Yinghai Lu, Hai Zhou: An efficient algorithm for library-based cell-type selection in high-performance low-power designs. ICCAD 2012: 226-232
- [c88]Yinghai Lu, Hai Zhou: Efficient design space exploration for component-based system design. ICCAD 2012: 466-472
- 2011
- [j40]Hai Zhou, Kevin Sparks, Nandu Gopalakrishnan, Pantelis Monogioudis, Francis Dominique, Peter Busschbach, Jim Seymour: Deprioritization of heavy users in wireless networks. IEEE Communications Magazine 49(10): 110-117 (2011)
- [j39]Min Gong, Hai Zhou, Li Li, Jun Tao, Xuan Zeng: Binning Optimization for Transparently-Latched Circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 30(2): 270-283 (2011)
- [j38]Chunyang Feng, Hai Zhou, Changhao Yan, Jun Tao, Xuan Zeng: Efficient Approximation Algorithms for Chemical Mechanical Polishing Dummy Fill. IEEE Trans. on CAD of Integrated Circuits and Systems 30(3): 402-415 (2011)
- [j37]Qiang Ma, Zaichen Qian, Evangeline F. Y. Young, Hai Zhou: MSV-Driven Floorplanning. IEEE Trans. on CAD of Integrated Circuits and Systems 30(8): 1152-1162 (2011)
- [j36]Kurt Keutzer, Peng Li, Li Shang, Hai Zhou: A Special Section on Multicore Parallel CAD: Algorithm Design and Programming. ACM Trans. Design Autom. Electr. Syst. 16(3): 21 (2011)
- [j35]Debasish Das, Ahmed Shebaita, Hai Zhou, Yehea I. Ismail, Kip Killpack: FA-STAC: An Algorithmic Framework for Fast and Accurate Coupling Aware Static Timing Analysis. IEEE Trans. VLSI Syst. 19(3): 443-456 (2011)
- [c87]James Williamson, Yinghai Lu, Li Shang, Hai Zhou, Xuan Zeng: Parallel cross-layer optimization of high-level synthesis and physical design. ASP-DAC 2011: 467-472
- [c86]Li Li, Jian Sun, Yinghai Lu, Hai Zhou, Xuan Zeng: Low power discrete voltage assignment under clock skew scheduling. ASP-DAC 2011: 515-520
- [c85]Yanling Zhi, Hai Zhou, Xuan Zeng: A practical method for multi-domain clock skew optimization. ASP-DAC 2011: 521-526
- [c84]Jian Sun, Yinghai Lu, Hai Zhou, Xuan Zeng: Post-routing layer assignment for double patterning. ASP-DAC 2011: 793-798
- [c83]
- [c82]Yuankai Chen, Hai Zhou, Robert P. Dick: Integrated circuit white space redistribution for temperature optimization. DATE 2011: 613-618
- [c81]Yanling Zhi, Wai-Shing Luk, Hai Zhou, Changhao Yan, Hengliang Zhu, Xuan Zeng: An efficient algorithm for multi-domain clock skew scheduling. DATE 2011: 1364-1369
- 2010
- [j34]Debasish Das, Kip Killpack, Chandramouli V. Kashyap, Abhijit Jas, Hai Zhou: Pessimism Reduction in Coupling-Aware Static Timing Analysis Using Timing and Logic Filtering. IEEE Trans. on CAD of Integrated Circuits and Systems 29(3): 466-478 (2010)
- [j33]Yinghai Lu, Hai Zhou, Li Shang, Xuan Zeng: Multicore Parallelization of Min-Cost Flow for CAD Applications. IEEE Trans. on CAD of Integrated Circuits and Systems 29(10): 1546-1557 (2010)
- [c80]Debasish Das, Jia Wang, Hai Zhou: iRetILP: an efficient incremental algorithm for min-period retiming under general delay model. ASP-DAC 2010: 61-67
- [c79]Jia Wang, Kun Li, Qin Lv, Hai Zhou, Li Shang: Hybrid energy storage system integration for vehicles. ISLPED 2010: 369-374
2000 – 2009
- 2009
- [j32]T. Izumi, Hai Zhou, Zuowei Li: Optimal Design of Gear Ratios and Offset for Energy Conservation of an Articulated Manipulator. IEEE T. Automation Science and Engineering 6(3): 551-557 (2009)
- [j31]Jia Wang, Debasish Das, Hai Zhou: Gate Sizing by Lagrangian Relaxation Revisited. IEEE Trans. on CAD of Integrated Circuits and Systems 28(7): 1071-1084 (2009)
- [j30]Kurt Keutzer, Peng Li, Li Shang, Hai Zhou: ACM Transactions on Design Automation of Electronic Systems (TODAES) special section call for papers: Parallel CAD: Algorithm design and programming. ACM Trans. Design Autom. Electr. Syst. 15(1) (2009)
- [j29]DiaaEldin Khalil, Debjit Sinha, Hai Zhou, Yehea I. Ismail: A Timing-Dependent Power Estimation Framework Considering Coupling. IEEE Trans. VLSI Syst. 17(6): 843-847 (2009)
- [c78]
- [c77]Jia Wang, Hai Zhou: Risk aversion min-period retiming under process variations. ASP-DAC 2009: 480-485
- [c76]Nikolaos D. Liveris, Hai Zhou, Prithviraj Banerjee: Complete-k-distinguishability for retiming and resynthesis equivalence checking without restricting synthesis. ASP-DAC 2009: 636-641
- [c75]Yinghai Lu, Li Shang, Hai Zhou, Hengliang Zhu, Fan Yang, Xuan Zeng: Statistical reliability analysis under process variation and aging effects. DAC 2009: 514-519
- [c74]Chunyang Feng, Hai Zhou, Changhao Yan, Jun Tao, Xuan Zeng: Provably good and practically efficient algorithms for CMP dummy fill. DAC 2009: 539-544
- [c73]Yinghai Lu, Hai Zhou, Li Shang, Xuan Zeng: Multicore parallel min-cost flow algorithm for CAD applications. DAC 2009: 832-837
- [c72]Yao Zhao, Sagar Vemuri, Jiazhen Chen, Yan Chen, Hai Zhou, Zhi Fu: Exception triggered DoS attacks on wireless networks. DSN 2009: 13-22
- [c71]Hai Zhou: Retiming and resynthesis with sweep are complete for sequential transformation. FMCAD 2009: 192-197
- [c70]Min Gong, Hai Zhou, Jun Tao, Xuan Zeng: Binning optimization based on SSTA for transparently-latched circuits. ICCAD 2009: 328-335
- [c69]Debasish Das, William Scott, Shahin Nazarian, Hai Zhou: An efficient current-based logic cell model for crosstalk delay analysis. ISQED 2009: 627-633
- 2008
- [j28]Jieyi Long, Hai Zhou, Seda Ogrenci Memik: EBOARST: An Efficient Edge-Based Obstacle-Avoiding Rectilinear Steiner Tree Construction Algorithm. IEEE Trans. on CAD of Integrated Circuits and Systems 27(12): 2169-2182 (2008)
- [j27]Chiu-Wing Sham, Evangeline F. Y. Young, Hai Zhou: Optimizing wirelength and routability by searching alternative packings in floorplanning. ACM Trans. Design Autom. Electr. Syst. 13(1) (2008)
- [j26]Hai Zhou: A new efficient retiming algorithm derived by formal manipulation. ACM Trans. Design Autom. Electr. Syst. 13(1) (2008)
- [j25]Ruiming Chen, Hai Zhou: Fast Estimation of Timing Yield Bounds for Process Variations. IEEE Trans. VLSI Syst. 16(3): 241-248 (2008)
- [c68]Nikolaos D. Liveris, Hai Zhou, Prithviraj Banerjee: A dynamic-programming algorithm for reducing the energy consumption of pipelined System-Level streaming applications. ASP-DAC 2008: 42-48
- [c67]Debasish Das, Kip Killpack, Chandramouli V. Kashyap, Abhijit Jas, Hai Zhou: Pessimism reduction in coupling-aware static timing analysis using timing and logic filtering. ASP-DAC 2008: 486-491
- [c66]
- [c65]Nikolaos D. Liveris, Hai Zhou, Robert P. Dick, Prithviraj Banerjee: State space abstraction for parameterized self-stabilizing embedded systems. EMSOFT 2008: 11-20
- [c64]Jia Wang, Hai Zhou: Linear constraint graph for floorplan optimization with soft blocks. ICCAD 2008: 9-15
- [c63]Jieyi Long, Hai Zhou, Seda Ogrenci Memik: An O(nlogn) edge-based algorithm for obstacle-avoiding rectilinear steiner tree construction. ISPD 2008: 126-133
- [r4]
- [r3]
- [r2]
- [r1]
- 2007
- [j24]Arindam Mallik, Debjit Sinha, Prithviraj Banerjee, Hai Zhou: Low-Power Optimization by Smart Bit-Width Allocation in a SystemC-Based ASIC Design Environment. IEEE Trans. on CAD of Integrated Circuits and Systems 26(3): 447-455 (2007)
- [j23]Chuan Lin, Hai Zhou: Tradeoff Between Latch and Flop for Min-Period Sequential Circuit Designs With Crosstalk. IEEE Trans. on CAD of Integrated Circuits and Systems 26(7): 1222-1232 (2007)
- [j22]Jia Wang, Hai Zhou: Optimal Jumper Insertion for Antenna Avoidance Considering Antenna Charge Sharing. IEEE Trans. on CAD of Integrated Circuits and Systems 26(8): 1445-1453 (2007)
- [j21]Debjit Sinha, Hai Zhou, Narendra V. Shenoy: Advances in Computation of the Maximum of a Set of Gaussian Random Variables. IEEE Trans. on CAD of Integrated Circuits and Systems 26(8): 1522-1533 (2007)
- [j20]Zhenyu (Peter) Gu, Jia Wang, Robert P. Dick, Hai Zhou: Unified Incremental Physical-Level and High-Level Synthesis. IEEE Trans. on CAD of Integrated Circuits and Systems 26(9): 1576-1588 (2007)
- [j19]Ruiming Chen, Hai Zhou: An Effective Algorithm for Buffer Insertion in General Circuits Based on Network Flow. IEEE Trans. on CAD of Integrated Circuits and Systems 26(11): 2069-2073 (2007)
- [c62]Ruiming Chen, Hai Zhou: Fast Buffer Insertion for Yield Optimization Under Process Variations. ASP-DAC 2007: 19-24
- [c61]Ruiming Chen, Hai Zhou: New Block-Based Statistical Timing Analysis Approaches Without Moment Matching. ASP-DAC 2007: 462-467
- [c60]Nikolaos D. Liveris, Chuan Lin, J. Wang, Hai Zhou, Prithviraj Banerjee: Retiming for Synchronous Data Flow Graphs. ASP-DAC 2007: 480-485
- [c59]Chuan Lin, Hai Zhou: Clock Skew Scheduling with Delay Padding for Prescribed Skew Domains. ASP-DAC 2007: 541-546
- [c58]
- [c57]
- [c56]Debasish Das, Ahmed Shebaita, Yehea I. Ismail, Hai Zhou, Kip Killpack: NostraXtalk: a predictive framework for accurate static timing analysis in udsm vlsi circuits. ACM Great Lakes Symposium on VLSI 2007: 25-30
- [c55]Jia Wang, Ming-Yang Kao, Hai Zhou: Address generation for nanowire decoders. ACM Great Lakes Symposium on VLSI 2007: 525-528
- [c54]Jia Wang, Debasish Das, Hai Zhou: Gate sizing by Lagrangian relaxation revisited. ICCAD 2007: 111-118
- [c53]
- [c52]Pingqiang Zhou, Yuchun Ma, Zhuoyuan Li, Robert P. Dick, Li Shang, Hai Zhou, Xianlong Hong, Qiang Zhou: 3D-STAF: scalable temperature and leakage aware floorplanning for three-dimensional integrated circuits. ICCAD 2007: 590-597
- [c51]Debjit Sinha, Jianfeng Luo, Subramanian Rajagopalan, Shabbir H. Batterywala, Narendra V. Shenoy, Hai Zhou: Impact of Modern Process Technologies on the Electrical Parameters of Interconnects. VLSI Design 2007: 875-880
- [e2]Hai Zhou, Enrico Macii, Zhiyuan Yan, Yehia Massoud (Eds.): Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, Stresa, Lago Maggiore, Italy, March 11-13, 2007. ACM 2007, ISBN 978-1-59593-605-9
- 2006
- [j18]Debjit Sinha, Hai Zhou: Gate-size optimization under timing constraints for coupling-noise reduction. IEEE Trans. on CAD of Integrated Circuits and Systems 25(6): 1064-1074 (2006)
- [j17]Chuan Lin, Hai Zhou: Optimal wire retiming without binary search. IEEE Trans. on CAD of Integrated Circuits and Systems 25(9): 1577-1588 (2006)
- [j16]Ruiming Chen, Hai Zhou: Statistical timing verification for transparently latched circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 25(9): 1847-1855 (2006)
- [j15]Debjit Sinha, Hai Zhou: Statistical Timing Analysis With Coupling. IEEE Trans. on CAD of Integrated Circuits and Systems 25(12): 2965-2975 (2006)
- [j14]Ruiming Chen, Hai Zhou: An Efficient Data Structure for Maxplus Merge in Dynamic Programming. IEEE Trans. on CAD of Integrated Circuits and Systems 25(12): 3004-3009 (2006)
- [j13]Debjit Sinha, Narendra V. Shenoy, Hai Zhou: Statistical Timing Yield Optimization by Gate Sizing. IEEE Trans. VLSI Syst. 14(10): 1140-1146 (2006)
- [j12]Chuan Lin, Jia Wang, Hai Zhou: Clustering for Processing Rate Optimization. IEEE Trans. VLSI Syst. 14(11): 1264-1275 (2006)
- [c50]
- [c49]
- [c48]Arindam Mallik, Debjit Sinha, Prithviraj Banerjee, Hai Zhou: Smart bit-width allocation for low power optimization in a systemc based ASIC design environment. DATE 2006: 618-623
- [c47]Chuan Lin, Hai Zhou, Chris C. N. Chu: A revisit to floorplan optimization by Lagrangian relaxation. ICCAD 2006: 164-171
- [c46]Debjit Sinha, DiaaEldin Khalil, Yehea I. Ismail, Hai Zhou: A timing dependent power estimation framework considering coupling. ICCAD 2006: 401-407
- [c45]Debasish Das, Ahmed Shebaita, Hai Zhou, Yehea I. Ismail, Kip Killpack: FA-STAC: A Framework for Fast and Accurate Static Timing Analysis with Coupling. ICCD 2006
- [c44]Debjit Sinha, Hai Zhou, Narendra V. Shenoy: Advances in Computation of the Maximum of a Set of Random Variables. ISQED 2006: 306-311
- [c43]Jia Wang, Hai Zhou, Ping-Chih Wu: Processing Rate Optimization by Sequential System Floorplanning. ISQED 2006: 340-345
- [c42]Serkan Ozdemir, Debjit Sinha, Gokhan Memik, Jonathan Adams, Hai Zhou: Yield-Aware Cache Architectures. MICRO 2006: 15-25
- [e1]Gang Qu, Yehea I. Ismail, Narayanan Vijaykrishnan, Hai Zhou (Eds.): Proceedings of the 16th ACM Great Lakes Symposium on VLSI 2006, Philadelphia, PA, USA, April 30 - May 1, 2006. ACM 2006, ISBN 1-59593-347-6
- 2005
- [j11]Qi Zhu, Hai Zhou, Tong Jing, Xianlong Hong, Yang Yang: Spanning graph-based nonrectilinear steiner tree algorithms. IEEE Trans. on CAD of Integrated Circuits and Systems 24(7): 1066-1075 (2005)
- [j10]Chuan Lin, Hai Zhou: Wire retiming as fixpoint computation. IEEE Trans. VLSI Syst. 13(12): 1340-1348 (2005)
- [c41]Debjit Sinha, Hai Zhou: Yield driven gate sizing for coupling-noise reduction under uncertainty. ASP-DAC 2005: 192-197
- [c40]
- [c39]Jia Wang, Hai Zhou: Interconnect estimation without packing via ACG floorplans. ASP-DAC 2005: 1152-1155
- [c38]Nikolaos D. Liveris, Hai Zhou, Prithviraj Banerjee: An Efficient System-Level to RTL Verification Framework for Computation-Intensive Applications. Asian Test Symposium 2005: 28-33
- [c37]Xiaoyong Tang, Hai Zhou, Prithviraj Banerjee: Leakage power optimization with dual-Vth library in high-level synthesis. DAC 2005: 202-207
- [c36]Zhenyu (Peter) Gu, Jia Wang, Robert P. Dick, Hai Zhou: Incremental exploration of the combined physical and behavioral design space. DAC 2005: 208-213
- [c35]
- [c34]Ruiming Chen, Hai Zhou: Efficient algorithms for buffer insertion in general circuits based on network flow. ICCAD 2005: 322-326
- [c33]Chuan Lin, Hai Zhou: Trade-off between latch and flop for min-period sequential circuit designs with crosstalk. ICCAD 2005: 329-334
- [c32]Debjit Sinha, Hai Zhou: A unified framework for statistical timing analysis with coupling and multiple input switching. ICCAD 2005: 837-843
- [c31]Debjit Sinha, Narendra V. Shenoy, Hai Zhou: Statistical gate sizing for timing yield optimization. ICCAD 2005: 1037-1041
- [c30]Min Pan, Chris C. N. Chu, Hai Zhou: Timing yield estimation using statistical static timing analysis. ISCAS (3) 2005: 2461-2464
- 2004
- [j9]Hai Zhou: Efficient Steiner tree construction based on spanning graphs. IEEE Trans. on CAD of Integrated Circuits and Systems 23(5): 704-710 (2004)
- [j8]Hai Zhou, Chuan Lin: Retiming for wire pipelining in system-on-chip. IEEE Trans. on CAD of Integrated Circuits and Systems 23(9): 1338-1345 (2004)
- [c29]Qi Zhu, Hai Zhou, Tong Jing, Xianlong Hong, Yang Yang: Efficient octilinear Steiner tree construction based on spanning graphs. ASP-DAC 2004: 687-690
- [c28]
- [c27]Jia Wang, Hai Zhou: Minimal period retiming under process variations. ACM Great Lakes Symposium on VLSI 2004: 131-135
- [c26]Debjit Sinha, Hai Zhou: Gate sizing for crosstalk reduction under timing constraints by Lagrangian relaxation. ICCAD 2004: 14-19
- [c25]
- [c24]
- [c23]
- [c22]Ruiming Chen, Hai Zhou: A Flexible Data Structure for Efficient Buffer Insertion. ICCD 2004: 216-221
- [c21]
- [c20]Debjit Sinha, Hai Zhou, Chris C. N. Chu: Optimal gate sizing for coupling-noise reduction. ISPD 2004: 176-181
- 2003
- [j7]Anuj Goel, Khurram Sajid, Hai Zhou, Adnan Aziz, Vigyan Singhal: BDD Based Procedures for a Theory of Equality with Uninterpreted Functions. Formal Methods in System Design 22(3): 205-224 (2003)
- [j6]Hai Zhou: Timing analysis with crosstalk is a fixpoint on a complete lattice. IEEE Trans. on CAD of Integrated Circuits and Systems 22(9): 1261-1269 (2003)
- [c19]Chiu-Wing Sham, Evangeline F. Y. Young, Hai Zhou: Interconnect-driven floorplanning by searching alternative packings. ASP-DAC 2003: 417-422
- [c18]Hai Zhou: Timing Verification with Crosstalk for Transparently Latched Circuits. DATE 2003: 10056-10061
- [c17]
- [c16]
- 2002
- [j5]Hai Zhou, Narendra V. Shenoy, William Nicholls: Efficient minimum spanning tree construction without Delaunay triangulation. Inf. Process. Lett. 81(5): 271-276 (2002)
- [c15]Shabbir H. Batterywala, Narendra V. Shenoy, William Nicholls, Hai Zhou: Track assignment: a desirable intermediate step between global routing and detailed routing. ICCAD 2002: 59-66
- [c14]Hai Zhou: Clock schedule verification with crosstalk. Timing Issues in the Specification and Synthesis of Digital Systems 2002: 78-83
- 2001
- [j4]Hai Zhou, Adnan Aziz: Buffer minimization in pass transistor logic. IEEE Trans. on CAD of Integrated Circuits and Systems 20(5): 693-697 (2001)
- [c13]Hai Zhou, Narendra V. Shenoy, William Nicholls: Efficient minimum spanning tree construction without Delaunay triangulation. ASP-DAC 2001: 192-197
- [c12]Hai Zhou, Narendra V. Shenoy, William Nicholls: Timing Analysis with Crosstalk as Fixpoints on Complete Lattice. DAC 2001: 714-719
- 2000
- [j3]Hai Zhou, Martin D. F. Wong, I-Min Liu, Adnan Aziz: Simultaneous routing and buffer insertion with restrictions onbuffer locations. IEEE Trans. on CAD of Integrated Circuits and Systems 19(7): 819-824 (2000)
- [c11]
- [c10]
1990 – 1999
- 1999
- [j2]Hai Zhou, Martin D. F. Wong: Global routing with crosstalk constraints. IEEE Trans. on CAD of Integrated Circuits and Systems 18(11): 1683-1688 (1999)
- [c9]Hai Zhou, D. F. Wong, I-Min Liu, Adnan Aziz: Simultaneous Routing and Buffer Insertion with Restrictions on Buffer Locations. DAC 1999: 96-99
- [c8]Hung-Ming Chen, Hai Zhou, Fung Yu Young, D. F. Wong, Hannah Honghua Yang, Naveed A. Sherwani: Integrated floorplanning and interconnect planning. ICCAD 1999: 354-357
- [c7]I-Min Liu, Adnan Aziz, D. F. Wong, Hai Zhou: An Efficient Buffer Insertion Algorithm for Large Networks Based on Lagrangian Relaxation. ICCD 1999: 210-215
- 1998
- [j1]Hai Zhou, D. F. Wong: Optimal river routing with crosstalk constraints. ACM Trans. Design Autom. Electr. Syst. 3(3): 496-514 (1998)
- [c6]Anuj Goel, Khurram Sajid, Hai Zhou, Adnan Aziz, Vigyan Singhal: BDD Based Procedures for a Theory of Equality with Uninterpreted Functions. CAV 1998: 244-255
- [c5]
- 1997
- [c4]Hai Zhou, D. F. Wong: An exact gate decomposition algorithm for low-power technology mapping. ICCAD 1997: 575-580
- [c3]Hai Zhou, D. F. Wong: Crosstalk-Constrained Maze Routing Based on Lagrangian Relaxation. ICCD 1997: 628-633
- 1996
- [c2]Chung-Ping Chen, Hai Zhou, D. F. Wong: Optimal non-uniform wire-sizing under the Elmore delay model. ICCAD 1996: 38-43
- [c1]Hai Zhou, D. F. Wong: An optimal algorithm for river routing with crosstalk constraints. ICCAD 1996: 310-315
Coauthor Index
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last updated on 2013-06-19 22:00 CEST by the dblp team