Xiaochun Zhu

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	2012
j1		Wenqing Wu, Xiaochun Zhu, Seung H. Kang, Kendrick Yuen, Rob Gilmore: Probabilistically Programmed STT-MRAM. IEEE J. Emerg. Sel. Topics Circuits Syst. 2(1): 42-51 (2012)
	2011
c9		Peiyuan Wang, Xiang Chen, Yiran Chen, Hai Helen Li, Seung H. Kang, Xiaochun Zhu, Wenqing Wu: A 1.0V 45nm nonvolatile magnetic latch design and its robustness analysis. CICC 2011: 1-4
c8		Cong Xu, Dimin Niu, Xiaochun Zhu, Seung H. Kang, Matt Nowak, Yuan Xie: Device-architecture co-optimization of STT-RAM based memory for low power embedded systems. ICCAD 2011: 463-470
c7		Zhenyu Sun, Xiuyuan Bi, Hai Helen Li, Weng-Fai Wong, Zhong-Liang Ong, Xiaochun Zhu, Wenqing Wu: Multi retention level STT-RAM cache designs with a dynamic refresh scheme. MICRO 2011: 329-338
	2009
c6		Fan Wang, Xiaohu Yang, Xiaochun Zhu, Lu Chen: Simulation of the defect removal process with queuing theory. ESEM 2009: 473-476
c5		Xiaochun Zhu, Bo Zhou, Lu Chen: Software testing sizing in incremental development: A case study. ESEM 2009: 490-493
	2008
c4		Yi Qu, Bo Zhou, Xiaochun Zhu: Early Estimate the Size of Test Suites from Use Cases. APSEC 2008: 487-492
c3		Xiaochun Zhu, Bo Zhou, Fan Wang, Yi Qu, Lu Chen: Estimate Test Execution Effort at an Early Stage: An Empirical Study. CW 2008: 195-200
c2		Xiaochun Zhu, Bo Zhou, Li Hou, Junbo Chen, Lu Chen: An Experience-Based Approach for Test Execution Effort Estimation. ICYCS 2008: 1193-1198
	1991
c1		Wen Deng, Xiaochun Zhu: A Simulating System for NC Lathe. ITAMS 1991: 291-297

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