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 | 2012 | |
|---|---|---|
| j41 |      | Shuai Wang, Jie S. Hu, Sotirios G. Ziavras: Exploring branch target buffer access filtering for low-energy and high-performance microarchitectures. IET Computers & Digital Techniques 6(1): 50-58 (2012) |
| j40 | | Spiridon F. Beldianu, Christopher Dahlberg, Timothy Steele, Sotirios G. Ziavras: Versatile design of shared vector coprocessors for multicores. Microprocessors and Microsystems - Embedded Hardware Design 36(7): 543-554 (2012) |
| j39 | | Shuai Wang, Jie S. Hu, Sotirios G. Ziavras: Replicating Tag Entries for Reliability Enhancement in Cache Tag Arrays. IEEE Trans. VLSI Syst. 20(4): 643-654 (2012) |
| j38 | | Imtiaz Sajid, M. M. Ahmed, Sotirios G. Ziavras: Novel Pipelined Architecture for Efficient Evaluation of the Square Root Using a Modified Non-Restoring Algorithm. Signal Processing Systems 67(2): 157-166 (2012) |
| c48 | | |
| 2011 | ||
| c47 | | Spiridon F. Beldianu, Sotirios G. Ziavras: On-chip Vector Coprocessor Sharing for Multicores. PDP 2011: 431-438 |
| 2010 | ||
| j37 | | Nitesh B. Guinde, Sotirios G. Ziavras: Efficient hardware support for pattern matching in network intrusion detection. Computers & Security 29(7): 756-769 (2010) |
| j36 | | Spiridon F. Beldianu, Roberto Rojas-Cessa, Eiji Oki, Sotirios G. Ziavras: Scheduling for input-queued packet switches by a re-configurable parallel match evaluator. IEEE Communications Letters 14(4): 357-359 (2010) |
| j35 | | Sara Motahari, Sotirios G. Ziavras, Quentin Jones: Online anonymity protection in computer-mediated communication. IEEE Transactions on Information Forensics and Security 5(3): 570-580 (2010) |
| c46 | | Imtiaz Sajid, Sotirios G. Ziavras, M. M. Ahmed: Hardware-Based Speed Up of Face Recognition Towards Real-Time Performance. DSD 2010: 763-770 |
| c45 | | Shuai Wang, Jie S. Hu, Sotirios G. Ziavras: TRB: Tag Replication Buffer for Enhancing the Reliability of the Cache Tag Array. ISVLSI 2010: 310-315 |
| c44 |  | Imtiaz Sajid, Sotirios G. Ziavras, M. M. Ahmed: FPGA-based Normalization for Modified Gram-Schmidt Orthogonalization. VISAPP (2) 2010: 227-232 |
| c43 | | Nitesh B. Guinde, Sotirios G. Ziavras: Novel FPGA-Based Signature Matching for Deep Packet Inspection. WISTP 2010: 261-276 |
| 2009 | ||
| j34 | | Muhammad Z. Hasan, Sotirios G. Ziavras: Customized kernel execution on reconfigurable hardware for embedded applications. Microprocessors and Microsystems - Embedded Hardware Design 33(3): 211-220 (2009) |
| j33 | | Shuai Wang, Jie S. Hu, Sotirios G. Ziavras: On the Characterization and Optimization of On-Chip Cache Reliability against Soft Errors. IEEE Trans. Computers 58(9): 1171-1184 (2009) |
| j32 | | Jie S. Hu, Shuai Wang, Sotirios G. Ziavras: On the Exploitation of Narrow-Width Values for Improving Register File Reliability. IEEE Trans. VLSI Syst. 17(7): 953-963 (2009) |
| c42 | | Sara Motahari, Sotirios G. Ziavras, Mor Naaman, Mohamed Ismail, Quentin Jones: Social Inference Risk Modeling in Mobile and Social Applications. CSE (3) 2009: 125-132 |
| c41 | | Shuai Wang, Jie S. Hu, Sotirios G. Ziavras, Sung Woo Chung: Exploiting narrow-width values for thermal-aware register file designs. DATE 2009: 1422-1427 |
| c40 | | Sara Motahari, Sotirios G. Ziavras, Richard P. Schuler, Quentin Jones: Identity Inference as a Privacy Risk in Computer-Mediated Communication. HICSS 2009: 1-10 |
| c39 | | Spiridon F. Beldianu, Roberto Rojas-Cessa, Eiji Oki, Sotirios G. Ziavras: Re-Configurable Parallel Match Evaluators Applied to Scheduling Schemes for Input-Queued Packet Switches. ICCCN 2009: 1-6 |
| c38 | | Sara Motahari, Sotirios G. Ziavras, Quentin Jones: Preventing Unwanted Social Inferences with Classification Tree Analysis. ICTAI 2009: 500-507 |
| c37 | | Sara Motahari, Sotirios G. Ziavras, Quentin Jones: Designing for different levels of social inference risk. SOUPS 2009 |
| 2008 | ||
| j31 | | Xin Tang, Constantine N. Manikopoulos, Sotirios G. Ziavras: Generalized Anomaly Detection Model for Windows-based Malicious Program Behavior . I. J. Network Security 7(3): 428-435 (2008) |
| j30 | | Shuai Wang, Hongyan Yang, Jie S. Hu, Sotirios G. Ziavras: Asymmetrically banked value-aware register files for low-energy and high-performance. Microprocessors and Microsystems - Embedded Hardware Design 32(3): 171-182 (2008) |
| j29 | | Shuai Wang, Jie S. Hu, Sotirios G. Ziavras: Self-Adaptive Data Caches for Soft-Error Reliability. IEEE Trans. on CAD of Integrated Circuits and Systems 27(8): 1503-1507 (2008) |
| j28 | | Dejiang Jin, Sotirios G. Ziavras: Robust scalability analysis and SPM case studies. The Journal of Supercomputing 43(3): 199-223 (2008) |
| c36 | | Shuai Wang, Jie S. Hu, Sotirios G. Ziavras: BTB Access Filtering: A Low Energy and High Performance Design. ISVLSI 2008: 81-86 |
| 2007 | ||
| j27 | | Hongyan Yang, Sotirios G. Ziavras, Jie S. Hu: Reconfiguration support for vector operations. IJHPSA 1(2): 89-97 (2007) |
| j26 | | Sotirios G. Ziavras, Alexandros V. Gerbessiotis, Rohan Bafna: Coprocessor design to support MPI primitives in configurable multiprocessors. Integration 40(3): 235-252 (2007) |
| j25 | | Muhammad Z. Hasan, Sotirios G. Ziavras: Partially Reconfigurable Vector Processor for Embedded Applications. JCP 2(9): 60-66 (2007) |
| c35 | | Xiaofang Wang, Sotirios G. Ziavras, Jie S. Hu: Energy-Aware System Synthesis for Reconfigurable Chip Multiprocessors. ERSA 2007: 61-70 |
| c34 | | Muhammad Z. Hasan, Sotirios G. Ziavras: Resource management for dynamically-challenged reconfigurable systems. ETFA 2007: 119-126 |
| c33 | | Kanchan Devarakonda, Sotirios G. Ziavras, Roberto Rojas-Cessa: Measuring Network Parameters with Hardware Support. ICNS 2007: 2 |
| c32 | | Dejiang Jin, Sotirios G. Ziavras: A Study of Data Exchange Protocols for the Grid Computing Environment. ICNS 2007: 75 |
| c31 | | Xiaofang Wang, Sotirios G. Ziavras: Performance-Energy Tradeoffs for Matrix Multiplication on FPGA-Based Mixed-Mode Chip Multiprocessors. ISQED 2007: 386-391 |
| c30 | | Shuai Wang, Hongyan Yang, Jie S. Hu, Sotirios G. Ziavras: Asymmetrically Banked Value-Aware Register Files. ISVLSI 2007: 363-368 |
| c29 | | Hongyan Yang, Shuai Wang, Sotirios G. Ziavras, Jie S. Hu: Vector Processing Support for FPGA-Oriented High Performance Applications. ISVLSI 2007: 447-448 |
| c28 | | Muhammad Z. Hasan, Sotirios G. Ziavras: Runtime Partial Reconfiguration for Embedded Vector Processors. ITNG 2007: 983-988 |
| c27 | | Hongyan Yang, Sotirios G. Ziavras, Jie S. Hu: FPGA-based Vector Processing for Matrix Operations. ITNG 2007: 989-994 |
| 2006 | ||
| j24 | | Xizhen Xu, Sotirios G. Ziavras: A Coarse-Grain Hierarchical Technique for 2-Dimensional FFT on Configurable Parallel Computers. IEICE Transactions 89-D(2): 639-646 (2006) |
| c26 | | Jie S. Hu, Shuai Wang, Sotirios G. Ziavras: In-Register Duplication: Exploiting Narrow-Width Value for Improving Register File Reliability. DSN 2006: 281-290 |
| c25 | | Xiaofang Wang, Sotirios G. Ziavras: System-Level Energy Modeling for Heterogeneous Reconfigurable Chip Multiprocessors. ICCD 2006 |
| c24 | | Shuai Wang, Jie S. Hu, Sotirios G. Ziavras: On the Characterization of Data Cache Vulnerability in High-Performance Embedded Microprocessors. ICSAMOS 2006: 14-20 |
| 2005 | ||
| j23 | | Dejiang Jin, Sotirios G. Ziavras: Modeling distributed data representation and its effect on parallel data accesses. J. Parallel Distrib. Comput. 65(10): 1281-1289 (2005) |
| c23 | | Jie S. Hu, Greg M. Link, Johnsy K. John, Shuai Wang, Sotirios G. Ziavras: Resource-Driven Optimizations for Transient-Fault Detecting SuperScalar Microarchitectures. Asia-Pacific Computer Systems Architecture Conference 2005: 200-214 |
| c22 | | Xizhen Xu, Sotirios G. Ziavras, Tae-Gyu Chang: An FPGA-Based Parallel Accelerator for Matrix Multiplications in the Newton-Raphson Method. EUC 2005: 458-468 |
| c21 | | Muhammad Z. Hasan, Sotirios G. Ziavras: FPGA-Based Vector Processing for Solving Sparse Sets of Equations. FCCM 2005: 331-332 |
| c20 | | Xiaofang Wang, Sotirios G. Ziavras: A Framework for Dynamic Resource Assignment and Scheduling on Reconfigurable Mixed-Mode On-Chip Multiprocessors. FPT 2005: 51-58 |
| c19 | | Roberto Rojas-Cessa, Ziqian Dong, Sotirios G. Ziavras: Load-balanced CICB packet switch with support for long round-trip times. GLOBECOM 2005: 5 |
| c18 | | Johnsy K. John, Jie S. Hu, Sotirios G. Ziavras: Optimizing the Thermal Behavior of Subarrayed Data Caches. ICCD 2005: 625-630 |
| c17 | | |
| c16 | | Hongyan Yang, Sotirios G. Ziavras: FPGA-based vector processor for algebraic equation solvers. SoCC 2005: 115-116 |
| c15 | | |
| 2004 | ||
| j22 | | Xiaofang Wang, Sotirios G. Ziavras: Parallel LU factorization of sparse matrices on FPGA-based configurable computing engines. Concurrency and Computation: Practice and Experience 16(4): 319-343 (2004) |
| j21 | | Dejiang Jin, Sotirios G. Ziavras: A Super-Programming Technique for Large Sparse Matrix Multiplication on PC Clusters. IEICE Transactions 87-D(7): 1774-1781 (2004) |
| j20 | | Satchidanand G. Haridas, Sotirios G. Ziavras: FPGA implementation of a Cholesky algorithm for a shared-memory multiprocessor architecture. Parallel Algorithms Appl. 19(4): 211-226 (2004) |
| j19 | | Dejiang Jin, Sotirios G. Ziavras: A Super-Programming Approach for Mining Association Rules in Parallel on PC Clusters. IEEE Trans. Parallel Distrib. Syst. 15(9): 783-794 (2004) |
| c14 | | Xiaofang Wang, Sotirios G. Ziavras: A Configurable Multiprocessor and Dynamic Load Balancing for Parallel LU Factorization. IPDPS 2004 |
| 2003 | ||
| j18 | | Sotirios G. Ziavras, Qian Wang, Paraskevi Papathanasiou: Viable Architectures for High-Performance Computing. Comput. J. 46(1): 36-54 (2003) |
| j17 | | Sotirios G. Ziavras: Processor design based on dataflow concurrency. Microprocessors and Microsystems 27(4): 199-220 (2003) |
| c13 | | Xizhen Xu, Sotirios G. Ziavras: Iterative Methods for Solving Linear Systems of Equations on FPGA-Based Machines. Computers and Their Applications 2003: 472-475 |
| c12 | | Xiaofang Wang, Sotirios G. Ziavras: Performance optimization of an FPGA-based configurable multiprocessor for matrix operations. FPT 2003: 303-306 |
| c11 | | Dejiang Jin, Sotirios G. Ziavras: Load Balancing on PC Clusters with the Super-Programming Model. ICPP Workshops 2003: 63-70 |
| c10 | | Xiaofang Wang, Sotirios G. Ziavras: Parallel Direct Solution of Linear Equations on FPGA-Based Machines. IPDPS 2003: 113 |
| 2002 | ||
| j16 | | Segreen Ingersoll, Sotirios G. Ziavras: Dataflow computation with intelligent memories emulated on field-programmable gate arrays (FPGAs). Microprocessors and Microsystems 26(6): 263-280 (2002) |
| 2000 | ||
| j15 | | Sotirios G. Ziavras, Haim Grebel, Anthony T. Chronopoulos, Florent Marcelli: A new-generation parallel computer and its performance evaluation. Future Generation Comp. Syst. 17(3): 315-333 (2000) |
| c9 | | Sotirios G. Ziavras: Versatile Processor Design for Efficiency and High Performance. ISPAN 2000: 266-273 |
| 1999 | ||
| j14 | | Sotirios G. Ziavras, Sanjay Krishnamurthy: Evaluating the communications capabilities of the generalized hypercube interconnection network. Concurrency - Practice and Experience 11(6): 281-300 (1999) |
| c8 | | Qian Wang, Sotirios G. Ziavras: Network Embedding Techniques for a New Class of Feasible Parallel Architectures. Applied Informatics 1999: 566-568 |
| c7 | | Qian Wang, Sotirios G. Ziavras: Powerful and Feasible Processor Interconnections With an Evaluation of Their Communications Capabilities. ISPAN 1999: 222-229 |
| 1997 | ||
| j13 | | Xi Li, Sotirios G. Ziavras, Constantine N. Manikopoulos: Parallel generation of adaptive multiresolution structures for image processing. Concurrency - Practice and Experience 9(4): 241-254 (1997) |
| 1996 | ||
| j12 | | Xi Li, Sotirios G. Ziavras, Constantine N. Manikopoulos: Parallel DSP algorithms on TurboNet: an experimental system with hybrid message-passing/shared-memory architecture. Concurrency - Practice and Experience 8(5): 387-411 (1996) |
| j11 | | Sotirios G. Ziavras, Arup Mukherjee: Data Broadcasting and Reduction, Prefix Computation, and Sorting on Reduces Hypercube Parallel Computer. Parallel Computing 22(4): 595-606 (1996) |
| c6 | | Sotirios G. Ziavras: Performance Analysis for an Important Class of Parallel-Processing Networks. ISPAN 1996: 500-506 |
| 1995 | ||
| j10 | | Sotirios G. Ziavras, Michalis A. Sideras: Facilitating High-Performance Image Analysis on Reduced Hypercube (RH) Parallel Computers. IJPRAI 9(4): 679-698 (1995) |
| j9 | | Sotirios G. Ziavras: Scalable Multifolded Hypercubes for versatile Parallel Computers. Parallel Processing Letters 5: 241-250 (1995) |
| 1994 | ||
| j8 | | Sotirios G. Ziavras, Devenkumar P. Shah: High-performance emulation of hierarchical structures on hypercube supercomputers. Concurrency - Practice and Experience 6(2): 85-100 (1994) |
| j7 | | Sotirios G. Ziavras, Peter Meer: Adaptive Multiresolution Structures for Image Processing on Parallel Computers. J. Parallel Distrib. Comput. 23(3): 475-483 (1994) |
| j6 | | Sotirios G. Ziavras: RH: A Versatile Family of Reduced Hypercube Interconnection Networks. IEEE Trans. Parallel Distrib. Syst. 5(11): 1210-1220 (1994) |
| 1993 | ||
| j5 | | Sotirios G. Ziavras, Muhammad A. Siddiqui: Pyramid mappings onto hypercubes for computer vision: Connection machine comparative study. Concurrency - Practice and Experience 5(6): 471-489 (1993) |
| j4 | | Sotirios G. Ziavras: Connected component labelling on the BLITZEN massively parallel processor. Image Vision Comput. 11(10): 665-668 (1993) |
| j3 | | Sotirios G. Ziavras: Efficient Mapping Algorithms for a Class of Hierarchical Systems. IEEE Trans. Parallel Distrib. Syst. 4(11): 1230-1245 (1993) |
| 1992 | ||
| j2 | | Sotirios G. Ziavras: On the Problem of Expanding Hypercube-Based Systems. J. Parallel Distrib. Comput. 16(1): 41-53 (1992) |
| c5 | | Sotirios G. Ziavras: Connection Machine Results for Pyramid Embedding Algorithms. CONPAR 1992: 31-36 |
| c4 | | Nagasimha G. Haravu, Sotirios G. Ziavras: Processor Allocation for a Class of Hypercube-Like Supercomputers. SC 1992: 740-749 |
| 1990 | ||
| c3 | | Sotirios G. Ziavras: Techniques for Mapping Deterministic Algorithms onto Multi-Level Systems. ICPP (1) 1990: 226-233 |
| 1989 | ||
| c2 | | |
| 1988 | ||
| j1 | | Sotirios G. Ziavras, Nikitas A. Alexandridis: Improved algorithms for translation of pictures represented by leaf codes. Image Vision Comput. 6(1): 13-20 (1988) |
| 1986 | ||
| c1 | | Nikitas A. Alexandridis, Sotirios G. Ziavras, P. D. Tsanakas: Architectural Adaptations for Hierarchical Image Processing/Transmission. ICC 1986: 424-428 |
Colors in the list of coauthors
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