Daniel Ziener

Dirk Koch, Jim Torresen, Christian Beckhoff, Daniel Ziener, Christopher Dennl, Volker Breuer, Jürgen Teich, Michael Feilen, Walter Stechele: Partial Reconfiguration on FPGAs in Practice - Tools and Applications. ARCS Workshops 2012: 297-319

Christopher Dennl, Daniel Ziener, Jürgen Teich: On-the-fly Composition of FPGA-Based SQL Query Accelerators Using a Partially Reconfigurable Module Library. FCCM 2012: 45-52

Tobias Ziermann, Alexander Butiu, Jürgen Teich, Daniel Ziener: FPGA-based testbed for timing behavior evaluation of the Controller Area Network (CAN). ReConFig 2012: 1-6

Stefan Wildermann, Felix Reimann, Daniel Ziener, Jürgen Teich: Symbolic design space exploration for multi-mode reconfigurable systems. CODES+ISSS 2011: 129-138

Josef Angermeier, Daniel Ziener, Michael Glaß, Jürgen Teich: Stress-Aware Module Placement on Reconfigurable Devices. FPL 2011: 277-281

Stefan Wildermann, Jürgen Teich, Daniel Ziener: Unifying Partitioning and Placement for SAT-Based Exploration of Heterogeneous Reconfigurable SoCs. FPL 2011: 429-434

Josef Angermeier, Daniel Ziener, Michael Glaß, Jürgen Teich: Runtime stress-aware replica placement on reconfigurable devices under safety constraints. FPT 2011: 1-6

Tobias Ziermann, Bernhard Schmidt, Moritz Mühlenthaler, Daniel Ziener, Josef Angermeier, Jürgen Teich: An FPGA implementation of a threat-based strategy for Connect6. FPT 2011: 1-4

Daniel Ziener: Techniques for Increasing Security and Reliability of IP Cores Embedded in FPGA and ASIC Designs. University of Erlangen-Nuremberg 2010, isbn 978-3-86853-657-7, pp. 1-325

Matthias May, Norbert Wehn, Abdelmajid Bouajila, Johannes Zeppenfeld, Walter Stechele, Andreas Herkersdorf, Daniel Ziener, Jürgen Teich: A rapid prototyping system for error-resilient multi-processor systems-on-chip. DATE 2010: 375-380

Daniel Ziener, Florian Baueregger, Jürgen Teich: Using the Power Side Channel of FPGAs for Communication. FCCM 2010: 237-244

Daniel Ziener, Florian Baueregger, Jürgen Teich: Multiplexing Methods for Power Watermarking. HOST 2010: 36-41

Daniel Ziener, Jürgen Teich: Concepts for run-time and error-resilient control flow checking of embedded RISC CPUs. IJAACS 2(3): 256-275 (2009)

Daniel Ziener, Jürgen Teich: Power Signature Watermarking of IP Cores for FPGAs. Signal Processing Systems 51(1): 123-136 (2008)

Daniel Ziener, Jürgen Teich: Concepts for Autonomous Control Flow Checking for Embedded CPUs. ATC 2008: 234-248

Moritz Schmid, Daniel Ziener, Jürgen Teich: Netlist-level IP protection by watermarking for LUT-based FPGAs. FPT 2008: 209-216

Daniel Ziener, Stefan Assmus, Jürgen Teich: Identifying FPGA IP-Cores Based on Lookup Table Content Analysis. FPL 2006: 1-6

Daniel Ziener, Jürgen Teich: FPGA core watermarking based on power signature analysis. FPT 2006: 205-212