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Zeljko Zilic
2010 – today
- 2012
[j24]Mohammad Hossein Neishaburi, Zeljko Zilic: An infrastructure for debug using clusters of assertion-checkers. Microelectronics Reliability 52(11): 2781-2798 (2012)- [j23]Omid Sarbishei, Katarzyna Radecka, Zeljko Zilic: Analytical Optimization of Bit-Widths in Fixed-Point LTI Systems. IEEE Trans. on CAD of Integrated Circuits and Systems 31(3): 343-355 (2012)
- [j22]Atanu Chattopadhyay, Zeljko Zilic: Flexible and Reconfigurable Mismatch-Tolerant Serial Clock Distribution Networks. IEEE Trans. VLSI Syst. 20(3): 523-536 (2012)
- [c75]Atena Roshan Fekr, Majid Janidarmian, Omid Sarbishei, Benjamin Nahill, Katarzyna Radecka, Zeljko Zilic: MSE minimization and fault-tolerant data fusion for multi-sensor systems. ICCD 2012: 445-452
- [c74]Majid Janidarmian, Zeljko Zilic, Katarzyna Radecka: Issues in Multi-valued Multi-modal Sensor Fusion. ISMVL 2012: 238-243
- [c73]Jason G. Tong, Marc Bottle, Zeljko Zilic: Assertion clustering for compacted test sequence generation. ISQED 2012: 694-701
- [c72]Mohammad Hossein Neishaburi, Zeljko Zilic: An enhanced debug-aware network interface for Network-on-Chip. ISQED 2012: 709-716
- [c71]Luca Montesi, Zeljko Zilic, Takahiro Hanyu, Daisuke Suzuki: Building Blocks to Use in Innovative Non-volatile FPGA Architecture Based on MTJs. ISVLSI 2012: 302-307
- [c70]Edin Kadric, Naraig Manjikian, Zeljko Zilic: An FPGA implementation for a high-speed optical link with a PCIe interface. SoCC 2012: 83-87
- 2011
- [j21]Prabhat Mishra, Zeljko Zilic, Sandeep K. Shukla: Guest Editors' Introduction: Multicore SoC Validation with Transaction-Level Models. IEEE Design & Test of Computers 28(3): 6-9 (2011)
- [j20]Zeljko Zilic, Prabhat Mishra, Sandeep K. Shukla: Challenges of Rapidly Emerging Consumer Space Multiprocessors. IEEE Design & Test of Computers 28(3): 52-53 (2011)
- [j19]Sandeep K. Shukla, Prabhat Mishra, Zeljko Zilic: A Brief History of Multiprocessors and EDA. IEEE Design & Test of Computers 28(3): 96 (2011)
- [j18]Stephan Bourduas, Zeljko Zilic: Modeling and evaluation of ring-based interconnects for Network-on-Chip. Journal of Systems Architecture - Embedded Systems Design 57(1): 39-60 (2011)
- [c69]Yu Pang, Katarzyna Radecka, Zeljko Zilic: An efficient hybrid engine to perform range analysis and allocate integer bit-widths for arithmetic circuits. ASP-DAC 2011: 455-460
- [c68]Mohammad Hossein Neishaburi, Zeljko Zilic: Hierarchical Embedded Logic Analyzer for Accurate Root-Cause Analysis. DFT 2011: 120-128
- [c67]Mohammad Hossein Neishaburi, Zeljko Zilic: Debug Aware AXI-based Network Interface. DFT 2011: 399-407
- [c66]Mohammad Hossein Neishaburi, Zeljko Zilic: A Fault Tolerant Hierarchical Network on Chip Router Architecture. DFT 2011: 445-453
- [c65]Mohammad Hossein Neishaburi, Zeljko Zilic: On Failure Rate Assessment Using an Executable Model of the System. DSD 2011: 29-36
- [c64]Bojan Mihajlovic, Zeljko Zilic: Real-time address trace compression for emulated and real system-on-chip processor core debugging. ACM Great Lakes Symposium on VLSI 2011: 331-336
- [c63]Mohammad Hossein Neishaburi, Zeljko Zilic: ERAVC: Enhanced reliability aware NoC router. ISQED 2011: 591-596
- [c62]Zeljko Zilic, Boris Karajica: High-level design of integrated microsystems - arithmetic perspective. ROSE 2011: 77-82
- [c61]Mohammad Hossein Neishaburi, Zeljko Zilic: A distributed AXI-based platform for post-silicon validation. VTS 2011: 8-13
- [c60]Zeljko Zilic, Katarzyna Radecka: Fault tolerant glucose sensor readout and recalibration. Wireless Health 2011: 35
- [e1]Zeljko Zilic, Sandeep K. Shukla (Eds.): 2011 IEEE International High Level Design Validation and Test Workshop, HLDVT 2011, Napa Valley, CA, USA, November 9-11, 2011. IEEE 2011, ISBN 978-1-4577-1744-4
- 2010
- [j17]Yongquan Fan, Zeljko Zilic: Qualifying Serial Interface Jitter Rapidly and Cost-effectively. J. Electronic Testing 26(2): 177-193 (2010)
- [j16]Jason G. Tong, Marc Boule, Zeljko Zilic: Defining and Providing Coverage for Assertion-Based Dynamic Verification. J. Electronic Testing 26(2): 211-225 (2010)
- [j15]Yu Pang, Katarzyna Radecka, Zeljko Zilic: Optimization of Imprecise Circuits Represented by Taylor Series and Real-Valued Polynomials. IEEE Trans. on CAD of Integrated Circuits and Systems 29(8): 1177-1190 (2010)
- [j14]Katell Morin-Allory, Marc Boule, Dominique Borrione, Zeljko Zilic: Validating Assertion Language Rewrite Rules and Semantics With Automated Theorem Provers. IEEE Trans. on CAD of Integrated Circuits and Systems 29(9): 1436-1448 (2010)
- [c59]Mohammad Hossein Neishaburi, Zeljko Zilic: Enabling efficient post-silicon debug by clustering of hardware-assertions. DATE 2010: 985-988
- [c58]Omar Abdelfattah, Andraws Swidan, Zeljko Zilic: Direct residue-to-analog conversion scheme based on Chinese Remainder Theorem. ICECS 2010: 687-690
- [c57]Yu Pang, Katarzyna Radecka, Zeljko Zilic: An efficient method to perform range analysis for DSP circuits. ICECS 2010: 855-858
2000 – 2009
- 2009
- [c56]Ivan Bilicki, Vijay Sundaresan, Daryl Maier, Nikola Grcevski, Zeljko Zilic: Cache line reservation: exploring a scheme for cache-friendly object allocation. CASCON 2009: 247-260
- [c55]Atanu Chattopadhyay, Zeljko Zilic: Serial reconfigurable mismatch-tolerant clock distribution. DAC 2009: 611-612
- [c54]Yann Oddos, Katell Morin-Allory, Dominique Borrione, Marc Boule, Zeljko Zilic: MYGEN: automata-based on-line test generator for assertion-based verification. ACM Great Lakes Symposium on VLSI 2009: 75-80
- [c53]Mohammad Hossein Neishaburi, Zeljko Zilic: Reliability aware NoC router architecture using input channel buffer sharing. ACM Great Lakes Symposium on VLSI 2009: 511-516
- [c52]Jason G. Tong, Marc Boule, Zeljko Zilic: Airwolf-TG: A test generator for assertion-based dynamic verification. HLDVT 2009: 106-113
- [c51]Yongquan Fan, Zeljko Zilic: A versatile scheme for the validation, testing and debugging of High Speed Serial Interfaces. HLDVT 2009: 114-121
- [c50]Zeljko Zilic: Designing and Using FPGAs beyond Classical Binary Logic: Opportunities in Nano-Scale Integration Age. ISMVL 2009: 268-273
- [c49]Yongquan Fan, Zeljko Zilic: Accelerating jitter tolerance qualification for high speed serial interfaces. ISQED 2009: 360-365
- 2008
- [j13]Stephan Bourduas, Jean-Samuel Chenard, Zeljko Zilic: A Quality-Driven Design Approach for NoCs. IEEE Design & Test of Computers 25(5): 416-428 (2008)
- [j12]Jean-Samuel Chenard, Zeljko Zilic, Milos Prokic: A Laboratory Setup and Teaching Methodology for Wireless and Mobile Embedded Systems. IEEE Trans. Education 51(3): 378-384 (2008)
- [j11]Yongquan Fan, Zeljko Zilic: BER Testing of Communication Interfaces. IEEE T. Instrumentation and Measurement 57(5): 897-906 (2008)
- [j10]Marc Boule, Zeljko Zilic: Automata-based assertion-checker synthesis of PSL properties. ACM Trans. Design Autom. Electr. Syst. 13(1) (2008)
- [c48]Atanu Chattopadhyay, Zeljko Zilic: Built-in Clock Skew System for On-line Debug and Repair. DATE 2008: 248-251
- [c47]Katell Morin-Allory, Marc Boule, Dominique Borrione, Zeljko Zilic: Proving and disproving assertion rewrite rules with automated theorem provers. HLDVT 2008: 56-63
- 2007
- [j9]Marc Boule, Jean-Samuel Chenard, Zeljko Zilic: Debug enhancements in assertion-checker generation. IET Computers & Digital Techniques 1(6): 669-677 (2007)
- [j8]Zeljko Zilic, Katarzyna Radecka: Scaling and Better Approximating Quantum Fourier Transform by Higher Radices. IEEE Trans. Computers 56(2): 202-207 (2007)
- [c46]Stephan Bourduas, Zeljko Zilic: Latency Reduction of Global Traffic in Wormhole-Routed Meshes Using Hierarchical Rings for Global Routing. ASAP 2007: 302-307
- [c45]Marc Boule, Zeljko Zilic: Efficient Automata-Based Assertion-Checker Synthesis of SEREs for Hardware Emulation. ASP-DAC 2007: 324-329
- [c44]Henry H. Y. Chan, Zeljko Zilic: Modeling Simultaneous Switching Noise-Induced Jitter for System-on-Chip Phase-Locked Loops. DAC 2007: 430-435
- [c43]Zeljko Zilic, Katarzyna Radecka, Ali Kazamiphur: Reversible circuit technology mapping from non-reversible specifications. DATE 2007: 558-563
- [c42]
- [c41]Henry H. Y. Chan, Zeljko Zilic: A Performance Driven Layout Compaction Optimization Algorithm for Analog Circuits. ISCAS 2007: 2934-2937
- [c40]Marc Boule, Jean-Samuel Chenard, Zeljko Zilic: Assertion Checkers in Verification, Silicon Debug and In-Field Diagnosis. ISQED 2007: 613-620
- [c39]Yongquan Fan, Yi Cai, Zeljko Zilic: A high accuracy high throughput jitter test solution on ATE for 3GBPS and 6gbps serial-ata. ITC 2007: 1-10
- [c38]Stephan Bourduas, Zeljko Zilic: A Hybrid Ring/Mesh Interconnect for Network-on-Chip Using Hierarchical Rings for Global Routing. NOCS 2007: 195-204
- 2006
- [j7]Knockaert Radecka, Zeljko Zilic: Arithmetic transforms for compositions of sequential and imprecise datapaths. IEEE Trans. on CAD of Integrated Circuits and Systems 25(7): 1382-1391 (2006)
- [c37]Marc Boule, Zeljko Zilic: Efficient Automata-Based Assertion-Checker Synthesis of PSL Properties. HLDVT 2006: 69-76
- [c36]Marc Boule, Jean-Samuel Chenard, Zeljko Zilic: Adding Debug Enhancements to Assertion Checkers for Hardware Emulation and Silicon Debug. ICCD 2006
- [c35]Yongquan Fan, Yi Cai, Liming Fang, Anant Verma, William Burchanowski, Zeljko Zilic, Sandeep Kumar: An Accelerated Jitter Tolerance Test Technique on Ate for 1.5GB/S and 3GB/S Serial-ATA. ITC 2006: 1-10
- [c34]Rong Zhang, Zeljko Zilic, Katarzyna Radecka: Energy Efficient Software-Based Self-Test for Wireless Sensor Network Nodes. VTS 2006: 186-191
- 2005
- [j6]Atanu Chattopadhyay, Zeljko Zilic: GALDS: a complete framework for designing multiclock ASICs and SoCs. IEEE Trans. VLSI Syst. 13(6): 641-654 (2005)
- [c33]Jean-Samuel Chenard, Chun Yiu Chu, Zeljko Zilic, Milica Popovic: Design methodology for wireless nodes with printed antennas. DAC 2005: 291-296
- [c32]Marc Boule, Zeljko Zilic: Incorporating Ef.cient Assertion Checkers into Hardware Emulation. ICCD 2005: 221-228
- [c31]Henry H. Y. Chan, Zeljko Zilic: Modeling Layout Effects for Sensitivity-Based Analog Circuit Optimization. ISQED 2005: 390-395
- [c30]Jean-Samuel Chenard, Ahmed Usman Khalid, Milos Prokic, Rong Zhang, K.-L. Lim, Atanu Chattopadhyay, Zeljko Zilic: Expandable and Robust Laboratory for Microprocessor Systems. MSE 2005: 65-66
- 2004
- [j5]Katarzyna Radecka, Zeljko Zilic: Design Verification by Test Vectors and Arithmetic Transform Universal Test Set. IEEE Trans. Computers 53(5): 628-640 (2004)
- [c29]Ahmed Usman Khalid, Zeljko Zilic, Katarzyna Radecka: FPGA Emulation of Quantum Circuits. ICCD 2004: 310-315
- [c28]Yongquan Fan, Zeljko Zilic: A novel scheme of implementing high speed AWGN communication channel emulators in FPGAs. ISCAS (2) 2004: 877-880
- [c27]
- [c26]Henry H. Y. Chan, Zeljko Zilic: Estimating Phase-Locked Loop Jitter due to Substrate Coupling: A Cyclostationary Approach. ISQED 2004: 309-314
- [c25]Yongquan Fan, Zeljko Zilic, Man Wah Chiang: A Versatile High Speed Bit Error Rate Testing Scheme. ISQED 2004: 395-400
- [c24]Man Wah Chiang, Zeljko Zilic, Jean-Samuel Chenard, Katarzyna Radecka: Architectures of Increased Availability Wireless Sensor Network Nodes. ITC 2004: 1232-1241
- [c23]Kahn Li Lim, Zeljko Zilic: A novel phase detector for PAM-4 clock recovery in high speed serial links. SoCC 2004: 151-152
- 2003
- [c22]Yongquan Fan, Zeljko Zilic: Testing for bit error rate in FPGA communication interfaces. FPGA 2003: 243
- [c21]Atanu Chattopadhyay, Zeljko Zilic: A globally asynchronous locally dynamic system for ASICs and SoCs. ACM Great Lakes Symposium on VLSI 2003: 176-181
- [c20]Man Wah Chiang, Zeljko Zilic: Layered Approach to Designing System Test Interfaces. VTS 2003: 331-338
- 2002
- [j4]Marc Boule, Zeljko Zilic: An FPGA Move Generator for the Game of Chess. ICGA Journal 25(2): 85-94 (2002)
- [j3]Zeljko Zilic, Zvonko G. Vranesic: A Deterministic Multivariate Interpolation Algorithm for Small Finite Fields. IEEE Trans. Computers 51(9): 1100-1105 (2002)
- [c19]Stuart McCracken, Zeljko Zilic: FPGA test time reduction through a novel interconnect testing scheme. FPGA 2002: 136-144
- [c18]Katarzyna Radecka, Zeljko Zilic: Specifying and verifying imprecise sequential datapaths by Arithmetic Transforms. ICCAD 2002: 128-131
- [c17]Boris Polianskikh, Zeljko Zilic: Design and Implementation of Error Detection and Correction Circuitry for Multilevel Memory Protection. ISMVL 2002: 89-95
- [c16]Zeljko Zilic, Katarzyna Radecka: The Role of Super-Fast Transforms in Speeding Up Quantum Computations. ISMVL 2002: 129-135
- [c15]Katarzyna Radecka, Zeljko Zilic: Identifying Redundant Wire Replacements for Synthesis and Verification. VLSI Design 2002: 517-523
- 2001
- [c14]Katarzyna Radecka, Zeljko Zilic: Arithmetic Transforms for Verifying Compositions of Sequential Datapaths. ICCD 2001: 348-353
- [c13]Ian Brynjolfson, Zeljko Zilic: A new PLL design for clock management applications. ISCAS (4) 2001: 814-817
- [c12]Zeljko Zilic, Katarzyna Radecka: : Identifying redundant gate replacements in verification by error modeling. ITC 2001: 803-812
- 2000
- [c11]Ian Brynjolfson, Zeljko Zilic: FPGA clock management for low power applications (poster abstract). FPGA 2000: 219
- [c10]R. Grindley, Tarek S. Abdelrahman, Stephen Dean Brown, S. Caranci, D. DeVries, Benjamin Gamsa, A. Grbic, M. Gusat, R. Ho, Orran Krieger, Guy G. Lemieux, K. Loveless, Naraig Manjikian, P. McHardy, Sinisa Srbljic, Michael Stumm, Zvonko G. Vranesic, Zeljko Zilic: The NUMAchine Multiprocessor. ICPP 2000: 487-496
- [c9]Katarzyna Radecka, Zeljko Zilic: Using Arithmetic Transform for Verification of Datapath Circuits via Error Modeling. VTS 2000: 271-280
1990 – 1999
- 1999
- [c8]Zeljko Zilic, Katarzyna Radecka: On Feasible Multivariate Polynomial Interpolations over Arbitrary Fields. ISSAC 1999: 67-74
- [c7]
- 1998
- [j2]Zeljko Zilic, Zvonko G. Vranesic: Using Decision Diagrams to Design ULMs for FPGAs. IEEE Trans. Computers 47(9): 970-982 (1998)
- [c6]A. Grbic, Stephen Dean Brown, S. Caranci, R. Grindley, M. Gusat, Guy G. Lemieux, K. Loveless, Naraig Manjikian, Sinisa Srbljic, Michael Stumm, Zvonko G. Vranesic, Zeljko Zilic: Design and Implementation of the NUMAchine Multiprocessor. DAC 1998: 66-69
- 1996
- [c5]Stephen Dean Brown, Naraig Manjikian, Zvonko G. Vranesic, S. Caranci, A. Grbic, R. Grindley, M. Gusat, K. Loveless, Zeljko Zilic, Sinisa Srbljic: Experience in Designing a Large-scale Multiprocessor using Field-Programmable Devices and Advanced CAD Tools. DAC 1996: 427-432
- [c4]
- [c3]Zeljko Zilic, Zvonko G. Vranesic: New Interpolation Algorithms for Multiple-Valued Reed-Muller Forms. ISMVL 1996: 16-23
- 1995
- [j1]Zeljko Zilic, Zvonko G. Vranesic: A Multiple-Valued Reed-Muller Transform for Incompletely Specified Functions. IEEE Trans. Computers 44(8): 1012-1020 (1995)
- [c2]Zeljko Zilic, Zvonko G. Vranesic: Reed-Muller Forms for Incompletely Specified Functions via Sparse Polynomial Interpolation. ISMVL 1995: 36-43
- 1993
- [c1]
Coauthor Index
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last updated on 2013-01-11 20:48 CET by the dblp team