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Yervant Zorian
2010 – today
- 2012
[j74]P. Glenn Gulak, Rajesh Gupta, Gianluca Setti, Yervant Zorian: Message From the Steering Committee. IEEE Design & Test of Computers 29(1): 5 (2012)- [j73]Erik Jan Marinissen, Yervant Zorian: Guest Editorial: Special Issue on Testing of 3D Stacked Integrated Circuits. J. Electronic Testing 28(1): 13-14 (2012)
- [j72]Gurgen Harutyunyan, Samvel K. Shoukourian, Valery A. Vardanian, Yervant Zorian: A New Method for March Test Algorithm Generation and Its Application for Fault Detection in RAMs. IEEE Trans. on CAD of Integrated Circuits and Systems 31(6): 941-949 (2012)
- [c114]Yervant Zorian: Addressing Test Challenges in Advanced Technology Nodes. Asian Test Symposium 2012: 6
- [c113]Michael Nicolaidis, Lorena Anghel, Nacer-Eddine Zergainoh, Yervant Zorian, Tanay Karnik, Keith A. Bowman, James Tschanz, Shih-Lien Lu, Carlos Tokunaga, Arijit Raychowdhury, Muhammad M. Khellah, Jaydeep Kulkarni, Vivek De, Dimiter Avresky: Design for test and reliability in ultimate CMOS. DATE 2012: 677-682
- 2011
- [j71]Gurgen Harutunyan, Aram Hakhumyan, Samvel K. Shoukourian, Valery A. Vardanian, Yervant Zorian: Symmetry Measure for Memory Test and Its Application in BIST Optimization. J. Electronic Testing 27(6): 753-766 (2011)
- [j70]Víctor H. Champac, Fernanda Gusmão de Lima Kastensmidt, Leticia Maria Veiras Bolzani Poehls, Fabian Vargas, Yervant Zorian: 12th "IEEE Latin-American Test Workshop" Porto de Galinhas, Brazil, 27-30 March 2011. J. Low Power Electronics 7(4): 529-530 (2011)
- [c112]K. Darbinyan, Gurgen Harutyunyan, Samvel K. Shoukourian, Valery A. Vardanian, Yervant Zorian: A Robust Solution for Embedded Memory Test and Repair. Asian Test Symposium 2011: 461-462
- [c111]H. Grigoryan, Gurgen Harutunyan, Samvel K. Shoukourian, Valery A. Vardanian, Yervant Zorian: Generic BIST architecture for testing of content addressable memories. IOLTS 2011: 86-91
- [e1]Vladimir Hahanov, Yervant Zorian (Eds.): 9th East-West Design & Test Symposium, EWDTS 2011, Sevastopol, Ukraine, September 9-12, 2011. IEEE 2011, ISBN 978-1-4577-1957-8
- 2010
- [c110]H. Avetisyan, Gurgen Harutyunyan, Valery A. Vardanian, Yervant Zorian: An efficient March test for detection of all two-operation dynamic faults from subclass Sav. EWDTS 2010: 310-313
- [c109]
2000 – 2009
- 2009
- [j69]Erik Jan Marinissen, Yervant Zorian: Guest Editors' Introduction: The Status of IEEE Std 1500. IEEE Design & Test of Computers 26(1): 6-7 (2009)
- [j68]Erik Jan Marinissen, Yervant Zorian: IEEE Std 1500 Enables Modular SoC Testing. IEEE Design & Test of Computers 26(1): 8-17 (2009)
- [j67]Yervant Zorian: Guest Editor's Introduction: Examples of Management Decision Criteria. IEEE Design & Test of Computers 26(2): 6-7 (2009)
- [j66]Erik Jan Marinissen, Yervant Zorian: Guest Editors' Introduction: The Status of IEEE Std 1500 - Part 2. IEEE Design & Test of Computers 26(3): 4 (2009)
- [c108]Mark Redford, Joseph Sawicki, Prasad Subramaniam, Cliff Hou, Yervant Zorian, Kimon Michaels: DFM: don't care or competitive weapon? DAC 2009: 296-297
- [c107]
- [c106]Erik Jan Marinissen, Yervant Zorian: Testing 3D chips containing through-silicon vias. ITC 2009: 1-11
- 2008
- [j65]Alfredo Benso, Stefano Di Carlo, Paolo Prinetto, Yervant Zorian: IEEE Standard 1500 Compliance Verification for Embedded Cores. IEEE Trans. VLSI Syst. 16(4): 397-407 (2008)
- [c105]Gurgen Harutunyan, Valery A. Vardanian, Yervant Zorian: An Efficient March-Based Three-Phase Fault Location and Full Diagnosis Algorithm for Realistic Two-Operation Dynamic Faults in Random Access Memories. VTS 2008: 95-100
- 2007
- [j64]Gurgen Harutunyan, Valery A. Vardanian, Yervant Zorian: Minimal March Tests for Detection of Dynamic Faults in Random Access Memories. J. Electronic Testing 23(1): 55-74 (2007)
- [c104]Srikanth Venkataraman, Ruchir Puri, Steve Griffith, Ankush Oberai, Robert Madge, Greg Yeric, Walter Ng, Yervant Zorian: Making Manufacturing Work For You. DAC 2007: 107-108
- [c103]Gurgen Harutunyan, Valery A. Vardanian, Yervant Zorian: A March-based Fault Location Algorithm with Partial and Full Diagnosis for All Simple Static Faults in Random Access Memories. DDECS 2007: 145-148
- 2006
- [j63]Bruce C. Kim, Yervant Zorian: Guest Editors' Introduction: Big Innovations in Small Packages. IEEE Design & Test of Computers 23(3): 186-187 (2006)
- [c102]Ron Wilson, Yervant Zorian: Decision-making for complex SoCs in consumer electronic products. DAC 2006: 173
- [c101]Nic Mokhoff, Yervant Zorian: Tradeoffs and choices for emerging SoCs in high-end applications. DAC 2006: 273
- [c100]Gurgen Harutunyan, Valery A. Vardanian, Yervant Zorian: Minimal March-Based Fault Location Algorithm with Partial Diagnosis for all Static Faults in Random Access Memories. DDECS 2006: 262-267
- [c99]Gurgen Harutunyan, Valery A. Vardanian, Yervant Zorian: Minimal March Tests for Dynamic Faults in Random Access Memories. European Test Symposium 2006: 43-48
- [c98]Gurgen Harutunyan, Valery A. Vardanian, Yervant Zorian: Minimal March Test Algorithm for Detection of Linked Static Faults in Random Access Memories. VTS 2006: 120-127
- [c97]
- [c96]
- 2005
- [j62]
- [j61]Juan Antonio Carballo, Yervant Zorian, Raul Camposano, Andrzej J. Strojwas, John Kibarian, Dennis Wassung, Alex Alexanian, Steve Wigley, Neil Kelly: Guest Editors' Introduction: DFM Drives Changes in Design Flow. IEEE Design & Test of Computers 22(3): 200-205 (2005)
- [c95]
- [c94]Dennis Wassung, Yervant Zorian, Magdy S. Abadir, Mark Bapst, Colin Harris: Choosing flows and methodologies for SoC design. DAC 2005: 167
- [c93]Nic Mokhoff, Yervant Zorian, Kamalesh N. Ruparel, Hao Nham, Francesco Pessolano, Kee Sup Kim: How to determine the necessity for emerging solutions. DAC 2005: 274-275
- [c92]Yervant Zorian, Bill Frerichs, Dennis Wassung, Jim Ensel, Guri Stark, Mike Gianfagna, Kamalesh N. Ruparel: Semiconductor Industry Disaggregation vs Reaggregation: Who Will be the Shark? DATE 2005: 572
- [c91]Erik Jan Marinissen, Betty Prince, Doris Keitel-Schulz, Yervant Zorian: Challenges in Embedded Memory Design and Test. DATE 2005: 722-727
- [c90]Yervant Zorian, Valery A. Vardanian, K. Aleksanyan, K. Amirkhanyan: Impact of Soft Error Challenge on SoC Design. IOLTS 2005: 63-68
- [c89]Régis Leveugle, Yervant Zorian, Luca Breveglieri, André K. Nieuwland, Klaus Rothbart, Jean-Pierre Seifert: On-Line Testing for Secure Implementations: Design and Validation. IOLTS 2005: 211
- [c88]
- [c87]
- [c86]
- [c85]Gurgen Harutunyan, Valery A. Vardanian, Yervant Zorian: Minimal March Tests for Unlinked Static Faults in Random Access Memories. VTS 2005: 53-59
- [c84]Baosheng Wang, Yuejian Wu, Josh Yang, André Ivanov, Yervant Zorian: SRAM Retention Testing: Zero Incremental Time Integration with March Algorithms. VTS 2005: 66-71
- 2004
- [j60]Don Edenfeld, Andrew B. Kahng, Mike Rodgers, Yervant Zorian: 2003 Technology Roadmap for Semiconductors. IEEE Computer 37(1): 47-56 (2004)
- [j59]Yervant Zorian, Dimitris Gizopoulos, Cary Vandenberg, Philippe Magarshack: Guest Editors' Introduction: Design for Yield and Reliability. IEEE Design & Test of Computers 21(3): 177-182 (2004)
- [j58]Samvel K. Shoukourian, Valery A. Vardanian, Yervant Zorian: SoC Yield Optimization via an Embedded-Memory Test and Repair Infrastructure. IEEE Design & Test of Computers 21(3): 200-207 (2004)
- [j57]Debesh K. Das, Hideo Fujiwara, Yungang Li, Yinghua Min, Shiyi Xu, Yervant Zorian: Design & Test Education in Asia. IEEE Design & Test of Computers 21(4): 331-338 (2004)
- [j56]Rajesh Pendurkar, Abhijit Chatterjee, Yervant Zorian: Distributed Diagnosis of Interconnections in SoC and MCM Designs. J. Electronic Testing 20(3): 291-307 (2004)
- [j55]Irith Pomeranz, Yervant Zorian: Fault isolation for nonisolated blocks. IEEE Trans. VLSI Syst. 12(12): 1385-1388 (2004)
- [c83]
- [c82]N. Derhacobian, Valery A. Vardanian, Yervant Zorian: Embedded Memory Reliability: The SER Challenge. MTDT 2004: 104-110
- [c81]Baosheng Wang, Josh Yang, James Cicalo, André Ivanov, Yervant Zorian: Reducing Embedded SRAM Test Time under Redundancy Constraints. VTS 2004: 237-242
- [c80]Samvel K. Shoukourian, Valery A. Vardanian, Yervant Zorian: A Methodology for Design and Evaluation of Redundancy Allocation Algorithms. VTS 2004: 249-260
- 2003
- [j54]Yervant Zorian: Guest Editor's Introduction: Advances in Infrastructure IP. IEEE Design & Test of Computers 20(3): 49- (2003)
- [j53]Yervant Zorian, Samvel K. Shoukourian: Embedded-Memory Test and Repair: Infrastructure IP for SoC Yield. IEEE Design & Test of Computers 20(3): 58-66 (2003)
- [j52]Yervant Zorian: IEEE CASS becomes D&T Copublisher. IEEE Design & Test of Computers 20(3): 108- (2003)
- [j51]Alfredo Benso, Stefano Di Carlo, Paolo Prinetto, Yervant Zorian: A Hierarchical Infrastructure for SoC Test Management. IEEE Design & Test of Computers 20(4): 32-39 (2003)
- [j50]Nektarios Kranitis, Antonis M. Paschalis, Dimitris Gizopoulos, Yervant Zorian: Instruction-Based Self-Testing of Processor Cores. J. Electronic Testing 19(2): 103-112 (2003)
- [j49]Dimitris Gizopoulos, Mihalis Psarakis, Antonis M. Paschalis, Yervant Zorian: Easily Testable Cellular Carry Lookahead Adders. J. Electronic Testing 19(3): 285-298 (2003)
- [c79]
- [c78]Nektarios Kranitis, George Xenoulis, Dimitris Gizopoulos, Antonis M. Paschalis, Yervant Zorian: Low-Cost Software-Based Self-Testing of RISC Processor Cores. DATE 2003: 10714-10719
- [c77]Nektarios Kranitis, George Xenoulis, Antonis M. Paschalis, Dimitris Gizopoulos, Yervant Zorian: Application and Analysis of RT-Level Software-Based Self-Testing for Embedded Processor Cores. ITC 2003: 431-440
- [c76]Francisco DaSilva, Yervant Zorian, Lee Whetsel, Karim Arabi, Rohit Kapur: Overview of the IEEE P1500 Standard. ITC 2003: 988-997
- [c75]
- [c74]Irith Pomeranz, Sudhakar M. Reddy, Yervant Zorian: A Test Interface for Built-In Test of Non-Isolated Scanned Cores. VTS 2003: 371-378
- 2002
- [j48]Alan Allan, Don Edenfeld, William H. Joyner Jr., Andrew B. Kahng, Mike Rodgers, Yervant Zorian: 2001 Technology Roadmap for Semiconductors. IEEE Computer 35(1): 42-53 (2002)
- [j47]Erik Jan Marinissen, Rohit Kapur, Maurice Lousberg, Teresa L. McLaurin, Mike Ricchetti, Yervant Zorian: On IEEE P1500's Standard for Embedded Core Test. J. Electronic Testing 18(4-5): 365-383 (2002)
- [c73]
- [c72]Nektarios Kranitis, Antonis M. Paschalis, Dimitris Gizopoulos, Yervant Zorian: Effective Software Self-Test Methodology for Processor Cores. DATE 2002: 592-597
- [c71]Irith Pomeranz, Yervant Zorian: Fault Isolation Using Tests for Non-Isolated Blocks. DATE 2002: 1123
- [c70]Michel Renovell, Penelope Faure, Paolo Prinetto, Yervant Zorian: Testing the Unidimensional Interconnect Architecture of Symmetrical SRAM-Based FPGA. DELTA 2002: 297-301
- [c69]Valery A. Vardanian, Yervant Zorian: A March-Based Fault Location Algorithm for Static Random Access Memories. IOLTW 2002: 256-261
- [c68]
- [c67]Valery A. Vardanian, Yervant Zorian: A March-Based Fault Location Algorithm for Static Random Access Memories. MTDT 2002: 62-67
- [c66]Nektarios Kranitis, Antonis M. Paschalis, Dimitris Gizopoulos, Yervant Zorian: Instruction-Based Self-Testing of Processor Cores. VTS 2002: 223-228
- 2001
- [j46]
- [j45]
- [j44]
- [j43]Nektarios Kranitis, Antonis M. Paschalis, Dimitris Gizopoulos, Mihalis Psarakis, Yervant Zorian: An Effective Deterministic BIST Scheme for Shifter/Accumulator Pairs in Datapaths. J. Electronic Testing 17(2): 97-107 (2001)
- [j42]Michel Renovell, Jean Michel Portal, Penelope Faure, Joan Figueras, Yervant Zorian: A Discussion on Test Pattern Generation for FPGA - Implemented Circuits. J. Electronic Testing 17(3-4): 283-290 (2001)
- [j41]Koppolu Sasidhar, Abhijit Chatterjee, Yervant Zorian: Boundary Scan-Based Relay Wave Propagation Test of Arrays of Identical Structures. IEEE Trans. Computers 50(10): 1007-1019 (2001)
- [j40]Rajesh Pendurkar, Abhijit Chatterjee, Yervant Zorian: Switching activity generation with automated BIST synthesis forperformance testing of interconnects. IEEE Trans. on CAD of Integrated Circuits and Systems 20(9): 1143-1158 (2001)
- [c65]Yervant Zorian, Paolo Prinetto, João Paulo Teixeira, Isabel C. Teixeira, Carlos Eduardo Pereira, Octávio Páscoa Dias, Jorge Semião, Peter Muhmenthaler, W. Radermacher: Embedded tutorial: TRP: integrating embedded test and ATE. DATE 2001: 34-37
- [c64]Antonis M. Paschalis, Dimitris Gizopoulos, Nektarios Kranitis, Mihalis Psarakis, Yervant Zorian: Deterministic software-based self-testing of embedded processor cores. DATE 2001: 92-96
- [c63]
- [c62]Nektarios Kranitis, Mihalis Psarakis, Dimitris Gizopoulos, Antonis M. Paschalis, Yervant Zorian: An Effective Deterministic BIST Scheme for Shifter/Accumulator Pairs in Datapaths. ISQED 2001: 343-349
- [c61]Michel Renovell, Penelope Faure, Jean Michel Portal, Joan Figueras, Yervant Zorian: IS-FPGA : a new symmetric FPGA architecture with implicit scan. ITC 2001: 924-931
- [c60]Samvel K. Shoukourian, Valery A. Vardanian, Yervant Zorian: An Approach for Evaluation of Redunancy Analysis Algorithms. MTDT 2001: 51-
- [c59]Mihalis Psarakis, Antonis M. Paschalis, Nektarios Kranitis, Dimitris Gizopoulos, Yervant Zorian: Robust and Low-Cost BIST Architectures for Sequential Fault Testing in Datapath Multipliers. VTS 2001: 15-21
- 2000
- [j39]
- [j38]
- [j37]
- [j36]Nektarios Kranitis, Dimitris Gizopoulos, Antonis M. Paschalis, Mihalis Psarakis, Yervant Zorian: Power-/Energy Efficient BIST Schemes for Processor Data Paths. IEEE Design & Test of Computers 17(4): 15-28 (2000)
- [j35]Alfredo Benso, Silvia Cataldo, Silvia Chiusano, Paolo Prinetto, Yervant Zorian: A High-Level EDA Environment for the Automatic Insertion of HD-BIST Structures. J. Electronic Testing 16(3): 179-184 (2000)
- [j34]Michel Renovell, Jean Michel Portal, Joan Figueras, Yervant Zorian: An Approach to Minimize the Test Configuration for the Logic Cells of the Xilinx XC4000 FPGAs Family. J. Electronic Testing 16(3): 289-299 (2000)
- [j33]Michel Renovell, Jean Michel Portal, Joan Figueras, Yervant Zorian: Testing the Local Interconnect Resources of SRAM-Based FPGA's. J. Electronic Testing 16(5): 513-520 (2000)
- [j32]Mihalis Psarakis, Dimitris Gizopoulos, Antonis M. Paschalis, Yervant Zorian: Sequential Fault Modeling and Test Pattern Generation for CMOS Iterative Logic Arrays. IEEE Trans. Computers 49(10): 1083-1099 (2000)
- [c58]Michel Renovell, Jean Michel Portal, Penelope Faure, Joan Figueras, Yervant Zorian: TOF: a tool for test pattern generation optimization of an FPGA application oriented test. Asian Test Symposium 2000: 323-328
- [c57]
- [c56]Yervant Zorian, Erik Jan Marinissen: System chip test: how will it impact your design? DAC 2000: 136-141
- [c55]Yervant Zorian, Michael Nicolaidis, Peter Muhmenthaler, David Y. Lepejian, Chris W. H. Strolenberg, Kees Veelenturf: Tutorial Statement. DATE 2000: 66
- [c54]Yervant Zorian: Yield Improvement and Repair Trade-Off for Large Embedded Memories. DATE 2000: 69-70
- [c53]Dimitris Gizopoulos, Nektarios Kranitis, Mihalis Psarakis, Antonis M. Paschalis, Yervant Zorian: Effective Low Power BIST for Datapaths. DATE 2000: 757
- [c52]
- [c51]
- [c50]Yervant Zorian, Erik Jan Marinissen, Rohit Kapur: On using IEEE P1500 SECT for test plug-n-play. ITC 2000: 770-777
- [c49]Michel Renovell, Yervant Zorian: Different experiments in test generation for XILINX FPGAs. ITC 2000: 854-862
- [c48]Alfredo Benso, Silvia Chiusano, Stefano Di Carlo, Paolo Prinetto, Fabio Ricciato, Maurizio Spadari, Yervant Zorian: HD/sup 2/BIST: a hierarchical framework for BIST scheduling, data patterns delivering and diagnosis in SoCs. ITC 2000: 892-901
- [c47]Yervant Zorian, Erik Jan Marinissen, Maurice Lousberg, Sandeep Kumar Goel: Wrapper design for embedded core test. ITC 2000: 911-920
- [c46]Dimitris Gizopoulos, Nektarios Kranitis, Mihalis Psarakis, Antonis M. Paschalis, Yervant Zorian: Low Power/Energy BIST Scheme for Datapaths. VTS 2000: 23-28
1990 – 1999
- 1999
- [j31]Yervant Zorian, Erik Jan Marinissen, Sujit Dey: Testing Embedded-Core-Based System Chips. IEEE Computer 32(6): 52-60 (1999)
- [j30]
- [j29]
- [j28]
- [j27]Michel Renovell, Jean Michel Portal, Joan Figueras, Yervant Zorian: SRAM-Based FPGAs: Testing the Embedded RAM Modules. J. Electronic Testing 14(1-2): 159-167 (1999)
- [j26]Dimitris Gizopoulos, Antonis M. Paschalis, Yervant Zorian: An Effective Built-In Self-Test Scheme for Parallel Multipliers. IEEE Trans. Computers 48(9): 936-950 (1999)
- [c45]Michel Renovell, Jean Michel Portal, Joan Figueras, Yervant Zorian: Minimizing the Number of Test Configurations for Different FPGA Families. Asian Test Symposium 1999: 363-368
- [c44]Antonis M. Paschalis, Nektarios Kranitis, Mihalis Psarakis, Dimitris Gizopoulos, Yervant Zorian: An Effective BIST Architecture for Fast Multiplier Cores. DATE 1999: 117-121
- [c43]Michael Nicolaidis, Yervant Zorian: Scaling Deeper to Submicron: On-Line Testing to the Rescue. DATE 1999: 432-
- [c42]Michel Renovell, Jean Michel Portal, Joan Figueras, Yervant Zorian: Testing the Configurable Interconnect/Logic Interface of SRAM-Based FPGA's. DATE 1999: 618-622
- [c41]Yervant Zorian, Erik Jan Marinissen, Rohit Kapur, Tony Taylor, Lee Whetsel: Towards a standard for embedded core test: an example. ITC 1999: 616-627
- [c40]Alfredo Benso, Silvia Cataldo, Silvia Chiusano, Paolo Prinetto, Yervant Zorian: HD-BIST: a hierarchical framework for BIST scheduling and diagnosis in SOCs. ITC 1999: 1038-1044
- [c39]Irith Pomeranz, Yervant Zorian: Testing of Non-Isolated Embedded Legacy Cores and their Surrounding Logic. VTS 1999: 41-48
- [c38]Mihalis Psarakis, Antonis M. Paschalis, Dimitris Gizopoulos, Yervant Zorian: An Effective BIST Architecture for Sequential Fault Testing in Array Multipliers. VTS 1999: 252-259
- 1998
- [j25]
- [j24]Dilip K. Bhavsar, Yervant Zorian: ITC 97 Panel Sessions. IEEE Design & Test of Computers 15(1): 7, 91 (1998)
- [j23]Michel Renovell, Jean Michel Portal, Joan Figueras, Yervant Zorian: Testing the Interconnect of RAM-Based FPGAs. IEEE Design & Test of Computers 15(1): 45-50 (1998)
- [j22]Meh-Ron Amerian, William D. Atwell Jr., Ian Burgess, Gary D. Fleeman, David Y. Lepejian, T. W. Williams, Farzad Zarrinfar, Yervant Zorian: A D&T Roundtable: Testing Mixed Logic and DRAM Chips. IEEE Design & Test of Computers 15(2): 86-92 (1998)
- [j21]
- [j20]Dimitris Gizopoulos, Antonis M. Paschalis, Yervant Zorian: Effective Built-In Self-Test for Booth Multipliers. IEEE Design & Test of Computers 15(3): 105-111 (1998)
- [j19]
- [j18]Michael Nicolaidis, Yervant Zorian: On-Line Testing for VLSI - A Compendium of Approaches. J. Electronic Testing 12(1-2): 7-20 (1998)
- [j17]Ricardo de Oliveira Duarte, Michael Nicolaidis, Hakim Bederr, Yervant Zorian: Efficient Totally Self-Checking Shifter Design. J. Electronic Testing 12(1-2): 29-39 (1998)
- [c37]Michel Renovell, Jean Michel Portal, Joan Figueras, Yervant Zorian: SRAM-Based FPGA's: Testing the Interconnect/Logic Interface. Asian Test Symposium 1998: 266-271
- [c36]
- [c35]Michel Renovell, Jean Michel Portal, Joan Figueras, Yervant Zorian: RAM-Based FPGA's: A Test Approach for the Configurable Logic. DATE 1998: 82-88
- [c34]Cecilia Metra, Michel Renovell, G. Mojoli, Jean Michel Portal, Sandro Pastore, Joan Figueras, Yervant Zorian, Davide Salvi, Giacomo R. Sechi: Novel Technique for Testing FPGAs. DATE 1998: 89-94
- [c33]T. Bogue, Michael Gössel, Helmut Jürgensen, Yervant Zorian: Built-In Self-Test with an Alternating Output. DATE 1998: 180-184
- [c32]Michel Renovell, Jean Michel Portal, Joan Figueras, Yervant Zorian: SRAM-Based FPGAs: A Fault Model for the Configurable Logig Modules. FPL 1998: 139-148
- [c31]
- [c30]Rajesh Pendurkar, Abhijit Chatterjee, Yervant Zorian: Synthesis of BIST hardware for performance testing of MCM interconnections. ICCAD 1998: 69-73
- [c29]Yervant Zorian, Erik Jan Marinissen, Sujit Dey: Testing embedded-core based system chips. ITC 1998: 130-143
- [c28]Rajesh Pendurkar, Abhijit Chatterjee, Yervant Zorian: A distributed BIST technique for diagnosis of MCM interconnections. ITC 1998: 214-221
- [c27]Michel Renovell, Jean Michel Portal, Joan Figueras, Yervant Zorian: SRAM-based FPGA's: testing the LUT/RAM modules. ITC 1998: 1102-1111
- [c26]Ilyoung Kim, Yervant Zorian, Goh Komoriya, Hai Pham, Frank P. Higgins, Jim L. Lewandowski: Built in self repair for embedded high density SRAM. ITC 1998: 1112-1119
- [c25]Mihalis Psarakis, Dimitris Gizopoulos, Antonis M. Paschalis, Yervant Zorian: Robustly Testable Array Multipliers under Realistic Sequential Cell Fault Model. VTS 1998: 152-157
- 1997
- [j16]Yervant Zorian, Rajesh K. Gupta: Design and Test of Core-Based Systems on Chips. IEEE Design & Test of Computers 14(4): 14- (1997)
- [j15]Rajesh K. Gupta, Yervant Zorian: Introducing Core-Based System Design. IEEE Design & Test of Computers 14(4): 15-25 (1997)
- [j14]
- [j13]Yervant Zorian: Fundamentals of MCM Testing and Design-for-Testability. J. Electronic Testing 10(1-2): 7-14 (1997)
- [j12]Yervant Zorian, Hakim Bederr: An Effective Multi-Chip BIST Scheme. J. Electronic Testing 10(1-2): 87-95 (1997)
- [c24]Michel Renovell, Jean Michel Portal, Joan Figueras, Yervant Zorian: Test Pattern and Test Configuration Generation Methodology for the Logic of RAM-Based FPGA. Asian Test Symposium 1997: 254-
- [c23]Christian Dufaza, Yervant Zorian: On the generation of pseudo-deterministic two-patterns test sequence with LFSRs. ED&TC 1997: 69-76
- [c22]Ricardo de Oliveira Duarte, Michael Nicolaidis, Hakim Bederr, Yervant Zorian: Fault-secure shifter design: results and implementations. ED&TC 1997: 335-341
- [c21]
- [c20]Dimitris Gizopoulos, Antonis M. Paschalis, Yervant Zorian, Mihalis Psarakis: An Effective BIST Scheme for Arithmetic Logic Units. ITC 1997: 868-877
- [c19]J. Borel, M. Cecchini, C. Malipeddi, Janusz Rajski, Yervant Zorian: Systems On Silicon: Design and Test Challenges. VTS 1997: 184-185
- [c18]Michel Renovell, Joan Figueras, Yervant Zorian: Test of RAM-based FPGA: methodology and application to the interconnect. VTS 1997: 230-237
- [c17]Vishwani D. Agrawal, Robert C. Aitken, J. Braden, Joan Figueras, S. Kumar, Hans-Joachim Wunderlich, Yervant Zorian: Power Dissipation During Testing: Should We Worry About it? VTS 1997: 456-457
- 1996
- [j11]Yervant Zorian, Jan Hlavicka: Guest Editors' Introduction: East Meets West. IEEE Design & Test of Computers 13(1): 5-7 (1996)
- [j10]
- [j9]Yervant Zorian, Tom Anderson, Yvon Savaria, Claude Thibeault, André Ivanov: Panel Summaries. IEEE Design & Test of Computers 13(3): 6, 110-112 (1996)
- [j8]Gil Philips, Yervant Zorian, Charles W. Rosenthal, Bozena Kaminska: Conference Reports. IEEE Design & Test of Computers 13(3): 8, 113-144 (1996)
- [j7]André Ivanov, Barry K. Tsuji, Yervant Zorian: Programmable BIST Space Compactors. IEEE Trans. Computers 45(12): 1393-1404 (1996)
- [c16]Dimitris Gizopoulos, Antonis M. Paschalis, Yervant Zorian: An Effective BIST Scheme for Datapaths. ITC 1996: 76-85
- [c15]Koppolu Sasidhar, Abhijit Chatterjee, Yervant Zorian: Optimal Multiple Chain Relay Testing Scheme for MCMs on Large Area Substrates. ITC 1996: 818-827
- 1995
- [j6]Sreejit Chakravarty, Ramalingam Sridhar, Shambhu J. Upadhyaya, Yervant Zorian, Gil Philips, Bozena Kaminska, Bernard Courtois: Conference Reports. IEEE Design & Test of Computers 12(4): 95-97 (1995)
- [j5]Chih-Jen Lin, Yervant Zorian, Sudipta Bhawmik: Integration of partial scan and built-in self-test. J. Electronic Testing 7(1-2): 125-137 (1995)
- [c14]Dimitris Gizopoulos, Antonis M. Paschalis, Yervant Zorian: An effective BIST scheme for carry-save and carry-propagate array multipliers. Asian Test Symposium 1995: 298-302
- [c13]Fabian Vargas, Michael Nicolaidis, Yervant Zorian: An Approach for Designing Total-Dose Tolerant MCMs Based on Current Monitoring. ITC 1995: 345-354
- [c12]Dimitris Gizopoulos, Antonis M. Paschalis, Yervant Zorian: An Effective BIST Scheme for Booth Multipliers. ITC 1995: 824-833
- 1994
- [j4]A. J. van de Goor, Yervant Zorian: Effective march algorithms for testing single-order addressed memories. J. Electronic Testing 5(4): 337-345 (1994)
- [c11]A. J. van de Goor, Yervant Zorian, Ivo Schanstra: Functional Tests for Ring-Address SRAM-type FIFOs. EDAC-ETC-EUROASIC 1994: 666
- [c10]Yervant Zorian, A. J. van de Goor, Ivo Schanstra: An Effective BIST Scheme for Ring-Address Type FIFOs. ITC 1994: 378-387
- [c9]Cecil A. Dean, Yervant Zorian: Do You Practice Safe Tests? What We Found Out About Your Habits. ITC 1994: 887-892
- [c8]Ad J. Van de Goor, Ivo Schanstra, Yervant Zorian: Fault models and tests for Ring Address Type FIFOs. VTS 1994: 300-305
- 1993
- [c7]
- [c6]Harold N. Scholz, Duane R. Aadsen, Yervant Zorian: A Method for Delay Fault Self-Testing of Macrocells. ITC 1993: 253-261
- [c5]Chih-Jen Lin, Yervant Zorian, Sudipta Bhawmik: PSBIST: A Partial-Scan Based Built-In Self-Test Scheme. ITC 1993: 507-516
- 1992
- [j3]Yervant Zorian, André Ivanov: An Effective BIST Scheme for ROM's. IEEE Trans. Computers 41(5): 646-653 (1992)
- [j2]André Ivanov, Yervant Zorian: Count-based BIST compaction schemes and aliasing probability computation. IEEE Trans. on CAD of Integrated Circuits and Systems 11(6): 768-777 (1992)
- [c4]Yervant Zorian: A Universal Testability Strategy for Multi-Chip Modules Based on BIST and Boundary-Scan. ICCD 1992: 59-66
- 1990
- [j1]Yervant Zorian, Vinod K. Agarwal: Optimizing error masking in BIST by output data modification. J. Electronic Testing 1(1): 59-71 (1990)
- [c3]André Ivanov, Yervant Zorian: Computing the Error Escape Probability in Count-Based Compaction Schemes. ICCAD 1990: 368-371
- [c2]
1980 – 1989
- 1984
- [c1]Yervant Zorian, Vinod K. Agarwal: Higher Certainty of Error Coverage by Output Data Modification. ITC 1984: 140-147
Coauthor Index
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last updated on 2013-05-25 21:23 CEST by the dblp team