Victor V. Zyuban

Dieter F. Wendel, Ronald N. Kalla, James D. Warnock, Robert Cargnoni, Sam G. Chu, Joachim G. Clabes, Daniel Dreps, David Hrusecky, Joshua Friedrich, Md. Saiful Islam, James A. Kahle, Jens Leenstra, Gaurav Mittal, Jose Paredes, Juergen Pille, Phillip J. Restle, Balaram Sinharoy, George Smith, William J. Starke, Scott Taylor, James Van Norstrand, Stephen Weitzel, Phillip G. Williams, Victor V. Zyuban: POWER7™, a Highly Parallel, Scalable Multi-Core High End Server Processor. J. Solid-State Circuits 46(1): 145-161 (2011)

Pradip Bose, Alper Buyuktosunoglu, Chen-Yong Cher, John A. Darringer, Meeta Sharma Gupta, Hendrik F. Hamann, Hans M. Jacobson, Prabhakar Kudva, Eren Kursun, Niti Madan, Indira Nair, Jude A. Rivers, Jeonghee Shin, Alan J. Weger, Victor V. Zyuban: Power-efficient, reliable microprocessor architectures: modeling and design methods. ACM Great Lakes Symposium on VLSI 2010: 299-304

Dieter F. Wendel, Ronald N. Kalla, Robert Cargnoni, Joachim G. Clabes, Joshua Friedrich, R. Frech, James A. Kahle, Balaram Sinharoy, William J. Starke, Scott Taylor, Steve Weitzel, Sam G. Chu, Md. Saiful Islam, Victor V. Zyuban: The implementation of POWER7^TM: A highly parallel and scalable multi-core high-end server processor. ISSCC 2010: 102-103

James D. Warnock, Leon J. Sigal, Dieter F. Wendel, K. Paul Muller, Joshua Friedrich, Victor V. Zyuban, Ethan H. Cannon, A. J. KleinOsowski: POWER7^TM local clocking and clocked storage elements. ISSCC 2010: 178-179

Matthew M. Ziegler, Victor V. Zyuban, George Gristede, Milena Vratonjic, Joshua Friedrich: The opportunity cost of low power design: a case study in circuit tuning. ISLPED 2009: 133-138

Milena Vratonjic, Matthew M. Ziegler, George Gristede, Victor V. Zyuban, Thomas Mitchell, Ee Cho, Chandu Visweswariah, Vojin G. Oklobdzija: A New Methodology for Power-Aware Transistor Sizing: Free Power Recovery (FPR). PATMOS 2009: 307-316

Jeonghee Shin, Victor V. Zyuban, Pradip Bose, Timothy Mark Pinkston: A Proactive Wearout Recovery Approach for Exploiting Microarchitectural Redundancy to Extend Cache SRAM Lifetime. ISCA 2008: 353-362

Jeonghee Shin, Victor V. Zyuban, Zhigang Hu, Jude A. Rivers, Pradip Bose: A Framework for Architecture-Level Lifetime Reliability Modeling. DSN 2007: 534-543

Hans M. Jacobson, Pradip Bose, Zhigang Hu, Alper Buyuktosunoglu, Victor V. Zyuban, Richard J. Eickemeyer, Lee Eisen, John Griswell, Doug Logan, Balaram Sinharoy, Joel M. Tendler: Stretching the Limits of Clock-Gating Efficiency in Server-Class Processors. HPCA 2005: 238-242

Rakesh Kumar, Victor V. Zyuban, Dean M. Tullsen: Interconnections in Multi-Core Architectures: Understanding Mechanisms, Overheads and Scaling. ISCA 2005: 408-419

Victor V. Zyuban, David Brooks, Viji Srinivasan, Michael Gschwind, Pradip Bose, Philip N. Strenski, Philip G. Emma: Integrated Analysis of Power and Performance for Pipelined Microprocessors. IEEE Trans. Computers 53(8): 1004-1016 (2004)

Victor V. Zyuban, Sameh W. Asaad, Thomas W. Fox, Anne-Marie Haen, Daniel Littrell, Jaime H. Moreno: Design methodology for semi custom processor cores. ACM Great Lakes Symposium on VLSI 2004: 448-452

Zhigang Hu, Alper Buyuktosunoglu, Viji Srinivasan, Victor V. Zyuban, Hans M. Jacobson, Pradip Bose: Microarchitectural techniques for power gating of execution units. ISLPED 2004: 32-37

Stephen V. Kosonocky, Azeez J. Bhavnagarwala, Kenneth Chin, George Gristede, Anne-Marie Haen, Wei Hwang, Mark B. Ketchen, Suhwan Kim, Daniel R. Knebel, Kevin W. Warren, Victor V. Zyuban: Low-power circuits and technology for wireless digital systems. IBM Journal of Research and Development 47(2-3): 283-298 (2003)

Jaime H. Moreno, Victor V. Zyuban, Uzi Shvadron, Fredy D. Neeser, Jeff H. Derby, Malcolm S. Ware, Krishnan Kailas, Ayal Zaks, Amir B. Geva, Shay Ben-David, Sameh W. Asaad, Thomas W. Fox, Daniel Littrell, Marina Biberstein, Dorit Naishlos, Hillery C. Hunter: An innovative low-power high-performance programmable signal processor for digital communications. IBM Journal of Research and Development 47(2-3): 299-326 (2003)

Victor V. Zyuban, Philip N. Strenski: Balancing hardware intensity in microprocessor pipelines. IBM Journal of Research and Development 47(5-6): 585-598 (2003)

Victor V. Zyuban: Optimization of scannable latches for low energy. IEEE Trans. VLSI Syst. 11(5): 778-788 (2003)

Victor V. Zyuban: Unified architecture level energy-efficiency metric. ACM Great Lakes Symposium on VLSI 2002: 24-29

Victor V. Zyuban, Stephen V. Kosonocky: Low power integrated scan-retention mechanism. ISLPED 2002: 98-102

Victor V. Zyuban, Philip N. Strenski: Unified methodology for resolving power-performance tradeoffs at the microarchitectural and circuit levels. ISLPED 2002: 166-171

Viji Srinivasan, David Brooks, Michael Gschwind, Pradip Bose, Victor V. Zyuban, Philip N. Strenski, Philip G. Emma: Optimizing pipelines for power and performance. MICRO 2002: 333-344

Pradip Bose, David Brooks, Alper Buyuktosunoglu, Peter W. Cook, K. Das, Philip G. Emma, Michael Gschwind, Hans M. Jacobson, Tejas Karkhanis, Prabhakar Kudva, Stanley Schuster, James E. Smith, Viji Srinivasan, Victor V. Zyuban, David H. Albonesi, Sandhya Dwarkadas: Early-Stage Definition of LPX: A Low Power Issue-Execute Processor. PACS 2002: 1-17

Victor V. Zyuban, Peter M. Kogge: Inherently Lower-Power High-Performance Superscalar Architectures. IEEE Trans. Computers 50(3): 268-285 (2001)

Victor V. Zyuban, D. Meltzer: Clocking strategies and scannable latches for low power appliacations. ISLPED 2001: 346-351

David Brooks, Pradip Bose, Stanley Schuster, Hans M. Jacobson, Prabhakar Kudva, Alper Buyuktosunoglu, John-David Wellman, Victor V. Zyuban, Manish Gupta, Peter W. Cook: Power-Aware Microarchitecture: Design and Modeling Challenges for Next-Generation Microprocessors. IEEE Micro 20(6): 26-44 (2000)

Victor V. Zyuban, Peter M. Kogge: Optimization of high-performance superscalar architectures for energy efficiency. ISLPED 2000: 84-89

Victor V. Zyuban, Peter M. Kogge: Application of STD to latch-power estimation. IEEE Trans. VLSI Syst. 7(1): 111-115 (1999)

Victor V. Zyuban, Peter M. Kogge: The energy complexity of register files. ISLPED 1998: 305-310